Semiconductor device and method for manufacturing the same

ABSTRACT

An object is, in a thin film transistor in which an oxide semiconductor is used as an active layer, to prevent change in composition, film quality, an interface, or the like of an oxide semiconductor region serving as an active layer, and to stabilize electrical characteristics of the thin film transistor. In a thin film transistor in which a first oxide semiconductor region is used as an active layer, a second oxide semiconductor region having lower electrical conductivity than the first oxide semiconductor region is formed between the first oxide semiconductor region and a protective insulating layer for the thin film transistor, whereby the second oxide semiconductor region serves as a protective layer for the first oxide semiconductor region; thus, change in composition or deterioration in film quality of the first oxide semiconductor region can be prevented, and electrical characteristics of the thin film transistor can be stabilized.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device using an oxide semiconductor, a display device using the semiconductor device, and a manufacturing method thereof.

2. Description of the Related Art

In recent years, liquid crystal display devices typified by liquid crystal displays are becoming widespread. As a liquid crystal display, an active matrix liquid crystal display device provided with pixels each including a thin film transistor (TFT) is often used. In a thin film transistor included in an active matrix liquid crystal display device, amorphous silicon or polycrystalline silicon is used as an active layer. Although a thin film transistor using amorphous silicon has low field effect mobility, it can be easily formed over a large-sized substrate such as a large glass substrate. On the other hand, although a thin film transistor using polycrystalline silicon has high field effect mobility, it takes an enormous amount of time to form the thin film transistor using polycrystalline silicon over a large-sized substrate such as a large glass substrate because a crystallization process such as laser annealing is needed.

In view of the foregoing, techniques in which a thin film transistor is manufactured using an oxide semiconductor instead of the above silicon material and applied to electronic devices or optical devices have attracted attention. For example, Patent Document 1 and Patent Document 2 disclose a technique in which a thin film transistor is manufactured using zinc oxide or an In—Ga—Zn—O-based oxide semiconductor for an oxide semiconductor layer and such a transistor is used as a switching element or the like of an image display device.

CITATION LIST Patent Document

-   [Patent Document 1] Japanese Published Patent Application No.     2007-123861 -   [Patent Document 2] Japanese Published Patent Application No.     2007-96055

Electrical characteristics of the above-described oxide semiconductor layer are greatly affected by composition, film quality, an interface, or the like of the oxide semiconductor layer. In addition, the composition, the film quality, the interface, or the like of the oxide semiconductor layer is easily changed by exposure to air and contact with a film containing impurities.

In order to prevent oxygen or moisture in air from entering an oxide semiconductor layer of a thin film transistor, a protective insulating layer formed using an oxide (silicon oxide), a nitride (silicon nitride) or the like containing silicon as its main component is provided over the oxide semiconductor layer.

However, only provision of the protective insulating layer containing silicon as its main component is insufficient for stabilizing composition, film quality, an interface, or the like of the oxide semiconductor layer.

Further, when a resist mask or a resist stripper which is formed for patterning the oxide semiconductor layer is in contact with the oxide semiconductor layer, the film quality or the composition of the oxide semiconductor layer may be changed.

As described above, in accordance with change in composition, film quality, an interface, or the like of an oxide semiconductor layer, a problem arises in that electrical characteristics of a thin film transistor using an oxide semiconductor layer are also changed.

SUMMARY OF THE INVENTION

According to an embodiment of the present invention, in forming a thin film transistor, a first oxide semiconductor region is used as an active layer, and a second oxide semiconductor region having lower electrical conductivity than the first oxide semiconductor region and serving as a protective layer for the first oxide semiconductor region is formed between the first oxide semiconductor region and a protective insulating layer for the thin film transistor.

An embodiment of the present invention is a semiconductor device including: a gate electrode layer; a gate insulating layer over the gate electrode layer; a source and drain electrode layers over the gate insulating layer; a first oxide semiconductor region over the source and drain electrode layers; and a second oxide semiconductor region over the first oxide semiconductor region, in which part of the first oxide semiconductor region is in contact with the gate insulating layer and side surface portions of the source and drain electrode layers, between the source and drain electrode layers; the electrical conductivity of the second oxide semiconductor region is lower than the electrical conductivity of the first oxide semiconductor region; and the first oxide semiconductor region and the source and drain electrode layers are electrically connected.

Another embodiment of the present invention is a semiconductor device including: a gate electrode layer; a gate insulating layer over the gate electrode layer; a source and drain electrode layers over the gate insulating layer; a buffer layer having n-type conductivity over the source and drain electrode layers; a first oxide semiconductor region over the buffer layer having n-type conductivity; and a second oxide semiconductor region over the first oxide semiconductor region, in which part of the first oxide semiconductor region is in contact with the gate insulating layer and side surface portions of the source and drain electrode layers, between the source and drain electrode layers; the carrier concentration of the buffer layer is higher than the carrier concentration of the first oxide semiconductor region; the electrical conductivity of the second oxide semiconductor region is lower than the electrical conductivity of the first oxide semiconductor region; the electrical conductivity of the buffer layer is higher than the electrical conductivity of the first oxide semiconductor region and the electrical conductivity of the second oxide semiconductor region; and the first oxide semiconductor region and top surfaces of the source and drain electrode layers are electrically connected through the buffer layer.

Another embodiment of the present invention is a semiconductor device including: a gate electrode layer; a gate insulating layer over the gate electrode layer; a source and drain electrode layers over the gate insulating layer; and an oxide semiconductor layer over the source and drain electrode layers, in which part of the oxide semiconductor layer is in contact with the gate insulating layer and side surface portions of the source and drain electrode layers, between the source and drain electrode layers; the oxide semiconductor layer is an oxide semiconductor layer containing at least one of indium, gallium, zinc, and tin; the part of the oxide semiconductor layer is in contact with the side surface portions of the source and drain electrode layers through an insulating layer; and the oxide semiconductor layer and the source and drain electrode layers are electrically connected.

Note that the first oxide semiconductor region, the second oxide semiconductor region, and the buffer layer preferably each contain at least one of indium, gallium, zinc, and tin. In addition, the density of oxygen-hole defects of the second oxide semiconductor region is preferably lower than the density of oxygen-hole defects of the first oxide semiconductor region. Further, the first oxide semiconductor region and the second oxide semiconductor region may be formed as different oxide semiconductor layers, or may be formed in the same oxide semiconductor layer.

Note that the electrical conductivity of the second oxide semiconductor region is preferably 1.0×10⁻⁸ S/cm or lower. The carrier concentration of the buffer layer is preferably 1×10¹⁸/cm³ or higher.

The part of the first oxide semiconductor region is preferably in contact with the side surface portions of the source and drain electrode layers through an oxide film. The oxide film is preferably formed by thermal oxidation, oxygen plasma treatment, or ozone water treatment.

Alternatively, the part of the first oxide semiconductor region is preferably in contact with the side surface portions of the source and drain electrode layers through a sidewall insulating layer. The sidewall insulating layer is preferably formed using a silicon film, a silicon oxide film, a silicon nitride oxide film, or a silicon oxynitride film.

Another embodiment of the present invention is a method for manufacturing a semiconductor device, including the steps of: forming a gate electrode layer over a substrate; forming a gate insulating layer over the gate electrode layer; forming a conductive film over the gate insulating layer; etching the conductive film to form a source and drain electrode layers; forming a first oxide semiconductor film over the gate insulating layer and the source and drain electrode layers by a sputtering method; forming a second oxide semiconductor film over the first oxide semiconductor film by a sputtering method; and etching the first oxide semiconductor film and the second oxide semiconductor film to form a first oxide semiconductor region and a second oxide semiconductor region, in which the first oxide semiconductor region is provided so that part of the first oxide semiconductor region is in contact with the gate insulating layer and side surface portions of the source and drain electrode layers, between the source and drain electrode layers; and the proportion of the flow rate of an oxygen gas in a film-forming gas for forming the second oxide semiconductor film is made higher than the proportion of the flow rate of an oxygen gas in a film-forming gas for forming the first oxide semiconductor film.

Note that the first oxide semiconductor film and the second oxide semiconductor film preferably each contain at least one of indium, gallium, zinc, and tin. Further, the first oxide semiconductor film and the second oxide semiconductor film may be formed in one step by increasing the flow rate of the oxygen gas. Furthermore, the proportion of the flow rate of the oxygen gas in the film-forming gas for forming the first oxide semiconductor film is preferably lower than 70 volume %, and the proportion of the flow rate of the oxygen gas in the film-forming gas for forming the second oxide semiconductor film is preferably 70 volume % or higher.

Note that the ordinal numbers such as “first” and “second” in this specification are used for convenience and do not denote the order of steps and the stacking order of layers. In addition, the ordinal numbers in this specification do not denote particular names which specify the invention.

Note that the semiconductor devices in this specification indicate all the devices which can operate by using semiconductor characteristics, and an electronic optical device, a semiconductor circuit, and an electronic device are all included in the semiconductor devices.

According to an embodiment of the present invention, in a thin film transistor in which a first oxide semiconductor region is used as an active layer, a second oxide semiconductor region having lower electrical conductivity than the first oxide semiconductor region and serving as a protective layer is formed between the first oxide semiconductor region and a protective insulating layer for the thin film transistor, whereby the second oxide semiconductor region can prevent change in composition or deterioration in film quality of the first oxide semiconductor region, and electrical characteristics of the thin film transistor can be stabilized.

By using the thin film transistor for a pixel portion and a driver circuit portion of a display device, a display device with high electrical characteristics and high reliability can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are diagrams illustrating a semiconductor device according to an embodiment of the present invention.

FIGS. 2A to 2D are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIGS. 3A to 3C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 7 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIGS. 8A-1, 8A-2, 8B-1, and 8B-2 are diagrams illustrating a semiconductor device according to an embodiment of the present invention.

FIG. 9 is a diagram illustrating a semiconductor device according to an embodiment of the present invention.

FIG. 10 is a diagram illustrating a semiconductor device according to an embodiment of the present invention.

FIGS. 11A to 11C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 12 is a graph showing measurement results of electrical conductivity of an oxide semiconductor layer.

FIG. 13 is a diagram illustrating a semiconductor device according to an embodiment of the present invention.

FIGS. 14A and 14B are block diagrams each illustrating a semiconductor device.

FIG. 15 is a diagram illustrating a configuration of a signal line driver circuit.

FIG. 16 is a timing chart illustrating operation of a signal line driver circuit.

FIG. 17 is a timing chart illustrating operation of a signal line driver circuit.

FIG. 18 is a diagram illustrating a configuration of a shift register.

FIG. 19 is a diagram illustrating a connection structure of a flip-flop in FIG. 18.

FIG. 20 is a diagram illustrating a pixel equivalent circuit of a semiconductor device according to an embodiment of the present invention.

FIGS. 21A to 21C are diagrams each illustrating a semiconductor device according to an embodiment of the present invention.

FIGS. 22A-1, 22A-2, and 22B are diagrams illustrating a semiconductor device according to an embodiment of the present invention.

FIG. 23 is a diagram illustrating a semiconductor device according to an embodiment of the present invention.

FIGS. 24A and 24B are diagrams illustrating a semiconductor device according to an embodiment of the present invention.

FIGS. 25A and 25B are diagrams each illustrating an example of a usage pattern of electronic paper.

FIG. 26 is an external view of an example of an electronic book reader.

FIG. 27A is an external view of an example of a television device and FIG. 27B is an external view of an example of a digital photo frame.

FIGS. 28A and 28B are external views each illustrating an example of an amusement machine.

FIGS. 29A and 29B are diagrams each illustrating an example of a mobile phone.

FIGS. 30A and 30B are diagrams each illustrating a semiconductor device according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments and an example of the present invention will be described with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the mode and detail can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not interpreted as being limited to the following description of the embodiments and example. Note that, in all the drawings for explaining the embodiments and example, the same portions or portions having the same functions are denoted by the same reference numerals, and the description thereof will be made only once.

Embodiment 1

In this embodiment, a structure of a thin film transistor is described with reference to FIGS. 1A and 1B.

A thin film transistor having a bottom gate structure of this embodiment is illustrated in FIGS. 1A and 1B. FIG. 1A is a cross-sectional view, and FIG. 1B is a plan view. FIG. 1A is a cross-sectional view along line A1-A2 of FIG. 1B.

In the thin film transistor illustrated in FIGS. 1A and 1B, a gate electrode layer 101 is provided over a substrate 100, a gate insulating layer 102 is provided over the gate electrode layer 101, a source and drain electrode layers 105 a and 105 b are provided over the gate insulating layer 102, a first oxide semiconductor region 103 is provided over the gate insulating layer 102 and the source and drain electrode layers 105 a and 105 b, and a second oxide semiconductor region 104 having lower electrical conductivity than the first oxide semiconductor region 103 is provided over the first oxide semiconductor region 103. Note that the first oxide semiconductor region 103 and the second oxide semiconductor region 104 may be formed in the same oxide semiconductor layer, or may be formed as different oxide semiconductor layers. Further, between the first oxide semiconductor region 103 and the second oxide semiconductor region 104, an intermediate region between oxide semiconductors, whose electrical conductivity is gradually or continuously changed, may be present. The intermediate region between the oxide semiconductors may be formed in the oxide semiconductor layer in which the first oxide semiconductor region 103 and the second oxide semiconductor region 104 are formed, or may be formed as an oxide semiconductor layer which is different from the first oxide semiconductor region 103 and the second oxide semiconductor region 104.

The gate electrode layer 101 is formed to have a single-layer structure or a stacked-layer structure using a metal material such as aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, or scandium; an alloy material containing any of these materials as its main component; or a nitride containing any of these materials. The gate electrode layer 101 is desirably formed using a low-resistance conductive material such as aluminum or copper; however, the low-resistance conductive material has disadvantages of low heat resistance and being easily eroded. Thus, the low-resistance conductive material is preferably used in combination with a heat-resistant conductive material. As the heat-resistant conductive material, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, or the like is used.

For example, as a stacked-layer structure of the gate electrode layer 101, a two-layer structure in which a molybdenum layer is stacked over an aluminum layer, a two-layer structure in which a molybdenum layer is stacked over a copper layer, a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is stacked over a copper layer, or a two-layer structure in which a titanium nitride layer and a molybdenum layer are stacked is preferable. Alternatively, a three-layer structure in which a tungsten layer or a tungsten nitride layer, an aluminum-silicon alloy layer or an aluminum-titanium alloy layer, and a titanium nitride layer or a titanium layer are stacked is preferably employed.

As an oxide semiconductor layer for forming the first oxide semiconductor region 103 and the second oxide semiconductor region 104, an oxide semiconductor including a material whose composition formula is represented as InMO₃ (ZnO)_(m) (m>0) is preferably used, and in particular, an In—Ga—Zn—O-based oxide semiconductor is preferably used. Note that M denotes one or more of metal elements selected from gallium (Ga), iron (Fe), nickel (Ni), manganese (Mn), and cobalt (Co). In addition to a case where only Ga is contained as M, there is a case where Ga and the above metal elements other than Ga; for example, Ga and Ni or Ga and Fe are contained as M. Moreover, in the oxide semiconductor, in some cases, a transition metal element such as Fe or Ni or an oxide of the transition metal is contained as an impurity element in addition to a metal element contained as M. In this specification, an oxide semiconductor including a material whose composition formula is represented as InMO₃ (ZnO)_(m) (m>0) where at least Ga is included as M is referred to as an In—Ga—Zn—O-based oxide semiconductor, and a thin film thereof is also referred to as an In—Ga—Zn—O-based non-single-crystal film.

An amorphous structure is observed in the In—Ga—Zn—O-based non-single-crystal film by X-ray diffraction (XRD). Note that heat treatment is performed on the In—Ga—Zn—O non-single-crystal film at 200° C. to 500° C., typically 300° C. to 400° C., for 10 minutes to 100 minutes after the film is formed by a sputtering method.

By using an In—Ga—Zn—O-based non-single-crystal film as an active layer of a thin film transistor, a thin film transistor having electrical characteristics such as an on/off ratio of greater than or equal to 10⁹ and a mobility of greater than or equal to 10 at a gate voltage of ±20 V can be manufactured.

However, an oxide semiconductor layer for forming the first oxide semiconductor region 103 and the second oxide semiconductor region 104 is not limited to an oxide semiconductor layer including a material whose composition formula is represented as InMO₃ (ZnO)_(m) (m>0) as long as it contains at least one of indium, gallium, zinc, and tin. For example, an oxide semiconductor layer formed using zinc oxide (ZnO), tin oxide (SnO), indium zinc oxide (IZO), indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), gallium-doped zinc oxide (GZO), or the like may be used.

The first oxide semiconductor region 103 is provided to be partly in contact with the gate insulating layer 102 and side surface portions of the source and drain electrode layers 105 a and 105 b, between the source and drain electrode layers 105 a and 105 b. The thickness of the first oxide semiconductor region 103 is set to 10 nm to 300 nm, preferably, 20 nm to 100 nm.

The electrical conductivity of the first oxide semiconductor region 103 is preferably 1.0×10⁻⁸ S/cm or higher. In addition, the electrical conductivity of the first oxide semiconductor region 103 is preferably lower than 1.0×10⁻³ S/cm. The range of the carrier concentration of the first oxide semiconductor region 103 is preferably lower than 1×10¹⁷/cm³ (more preferably, 1×10¹¹/cm³ or higher). When the carrier concentration of the first oxide semiconductor region 103 exceeds the above range, the thin film transistor has a risk of being normally-on.

Further, the sodium concentration of the first oxide semiconductor region 103 is 5×10¹⁹/cm³ or lower, preferably, 1×10¹⁸/cm³ or lower.

The second oxide semiconductor region 104 has lower electrical conductivity than the first oxide semiconductor region 103, and the electrical conductivity of the second oxide semiconductor region 104 is preferably lower than 1.0×10⁻⁸ S/cm. The density of oxygen-hole defects of the second oxide semiconductor region 104 is preferably lower than that of the first oxide semiconductor region 103. This is because the electrical conductivity of the oxide semiconductor is affected by the oxygen-hole defects in the oxide semiconductor. The thickness of the second oxide semiconductor region 104 is preferably greater than or equal to 5 nm and less than or equal to 1000 nm, more preferably, greater than or equal to 10 nm and less than or equal to 100 nm.

The proportion of the flow rate of an oxygen gas in the whole film-forming gas for forming the second oxide semiconductor region 104 by sputtering is made higher than that of an oxygen gas in the whole film-forming gas for forming the first oxide semiconductor region 103 by sputtering. Accordingly, the density of the oxygen-hole defects of the second oxide semiconductor region 104 is lower than that of the first oxide semiconductor region 103, and the electrical conductivity of the second oxide semiconductor region 104 can be lower. The second oxide semiconductor region 104 is preferably formed under a condition where the proportion of the flow rate of the oxygen gas in the whole film-forming gas is 70 volume % or higher. In addition, the first oxide semiconductor region 103 is preferably formed under a condition where the proportion of the flow rate of the oxygen gas in the whole film-forming gas is lower than 70 volume %.

The first oxide semiconductor region 103 and the second oxide semiconductor region 104 can be successively formed. Therefore, efficiency in manufacturing a display device and productivity can be improved. Further, by forming the first oxide semiconductor region 103 and the second oxide semiconductor region 104 successively, the first oxide semiconductor region 103 can be patterned without exposure of its top surface to air.

Alternatively, the first oxide semiconductor region 103 and the second oxide semiconductor region 104 may be formed in one step by increasing the flow rate of the oxygen gas. Accordingly, the electrical conductivity can be continuously changed through the first oxide semiconductor region 103 and the second oxide semiconductor region 104.

The first oxide semiconductor region 103 serves as an active layer of the thin film transistor. On the other hand, the second oxide semiconductor region 104 having lower electrical conductivity than the first oxide semiconductor region 103 serves as a protective layer for preventing the first oxide semiconductor region 103 from being exposed to air and from being in contact with a film containing impurities which change composition or film quality of an oxide semiconductor. Therefore, the first oxide semiconductor region 103 which includes a channel formation region and determines the electrical characteristics of the thin film transistor is in contact with the second oxide semiconductor region 104 whose composition and film quality are similar to those of the first oxide semiconductor region 103, whereby change in the composition, the film quality, the interface, or the like of the first oxide semiconductor region 103 due to impurities can be prevented. Although the second oxide semiconductor region 104 serving as a protective layer is in contact with a film containing impurities which change composition or film quality of an oxide semiconductor, the second oxide semiconductor region 104 has lower electrical conductivity than the first oxide semiconductor region 103. Thus, the electrical characteristics of the thin film transistor are not affected.

As described above, in a thin film transistor in which a first oxide semiconductor region is used as an active layer, a second oxide semiconductor region having lower electrical conductivity than the first oxide semiconductor region and serving as a protective layer is formed between the first oxide semiconductor region and a protective insulating layer for the thin film transistor, whereby change in composition or deterioration in film quality of the first oxide semiconductor region can be prevented, and electrical characteristics of the thin film transistor can be stabilized.

The source or drain electrode layer 105 a has a three-layer structure of a first conductive film 112 a, a second conductive film 113 a, and a third conductive film 114 a while the source or drain electrode layer 105 b has a three-layer structure of a first conductive film 112 b, a second conductive film 113 b, and a third conductive film 114 b. Each of the first conductive films 112 a and 112 b, the second conductive films 113 a and 113 b, and the third conductive films 114 a and 114 b can be formed using a metal material such as aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, or scandium; an alloy material containing any of these metal materials as its main component; or a nitride containing any of these metal materials. Each of the first conductive films 112 a and 112 b, the second conductive films 113 a and 113 b, and the third conductive films 114 a and 114 b is desirably formed using a low-resistance conductive material such as aluminum or copper; however, the low-resistance conductive material has disadvantages of low heat resistance and being easily eroded. Thus, the low-resistance conductive material is preferably used in combination with a heat-resistant conductive material. As the heat-resistant conductive material, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, or the like is used.

For example, it is preferable that the first conductive films 112 a and 112 b and the third conductive films 114 a and 114 b be formed using titanium that is a heat-resistant conductive material, and the second conductive films 113 a and 113 b be formed using an aluminum alloy containing neodymium that has low heat resistance. By such a structure, a low resistance property of aluminum is utilized and generation of a hillock can be reduced. Note that, in this embodiment, the source or drain electrode layer 105 a is formed to have a three-layer structure of the first conductive film 112 a, the second conductive film 113 a, and the third conductive film 114 a while the source or drain electrode layer 105 b is formed to have a three-layer structure of the first conductive film 112 b, the second conductive film 113 b, and the third conductive film 114 b; however, the source and drain electrode layers 105 a and 105 b are not limited to this structure. Thus, the source and drain electrode layers 105 a and 105 may have a single-layer structure, a two-layer structure, or a stacked structure of four or more layers.

In this manner, in the thin film transistor in which the first oxide semiconductor region is used as an active layer, the second oxide semiconductor region having lower electrical conductivity than the first oxide semiconductor region and serving as a protective layer is formed between the first oxide semiconductor region and the protective insulating layer for the thin film transistor, whereby change in the composition or deterioration in the film quality of the first oxide semiconductor region can be prevented, and the electrical characteristics of the thin film transistor can be stabilized.

Note that the structure described in this embodiment can be combined with any of the structures described in another embodiment as appropriate.

Embodiment 2

In this embodiment, a manufacturing process of a display device including the thin film transistor described in Embodiment 1 will be described with reference to FIGS. 2A to 2D, FIGS. 3A to 3C, FIG. 4, FIG. 5, FIG. 6, FIG. 7, FIGS. 8A-1, 8A-2, 8B-1, and 8B-2, and FIG. 9. FIGS. 2A to 2D and FIGS. 3A to 3C are cross-sectional views, and FIG. 4, FIG. 5, FIG. 6, and FIG. 7 are plan views. Line A1-A2 and line B1-B2 in each of FIG. 4, FIG. 5, FIG. 6, and FIG. 7 correspond to line A1-A2 and line B1-B2 in each of the cross-sectional views of FIGS. 2A to 2D and FIGS. 3A to 3C, respectively.

First, the substrate 100 is prepared. As the substrate 100, any of the following substrates can be used: non-alkaline glass substrates made of barium borosilicate glass, aluminoborosilicate glass, aluminosilicate glass, and the like by a fusion method or a float method; ceramic substrates; plastic substrates having heat resistance enough to withstand a process temperature of this manufacturing process; and the like. Alternatively, a metal substrate such as a stainless steel alloy substrate, provided with an insulating film over its surface, may also be used. The substrate 100 may have a size of 320 mm×400 mm, 370 mm×470 mm, 550 mm×650 mm, 600 mm×720 mm, 680 mm×880 mm, 730 mm×920 mm, 1000 mm×1200 mm, 1100 mm×1250 mm, 1150 mm×1300 mm, 1500 mm×1800 mm, 1900 mm×2200 mm, 2160 mm×2460 mm, 2400 mm×2800 mm, 2850 mm×3050 mm, or the like.

In addition, an insulating film as a base film may be formed over the substrate 100. The base film may be formed to have a single-layer structure or a stacked-layer structure of any of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a silicon nitride oxide film by a CVD method, a sputtering method, or the like. In the case where a substrate containing mobile ions such as a glass substrate is used as the substrate 100, a film containing nitrogen such as a silicon nitride film or a silicon nitride oxide film is used as the base film, whereby the mobile ions can be prevented from entering the oxide semiconductor layer.

Next, a conductive film for forming a gate wiring including the gate electrode layer 101, a capacitor wiring 108, and a first terminal 121 is formed over the entire area over the substrate 100 by a sputtering method or a vacuum evaporation method. Next, a first photolithography step is performed. A resist mask is formed, and an unnecessary portion is removed by etching to form wirings and an electrode (a gate wiring including the gate electrode layer 101, the capacitor wiring 108, and the first terminal 121). At that time, etching is preferably performed so that at least an end portion of the gate electrode layer 101 is tapered for prevention of disconnection. A cross-sectional view at this stage is illustrated in FIG. 2A. Note that a plan view at this stage corresponds to FIG. 4.

The gate wiring including the gate electrode layer 101, the capacitor wiring 108, and the first terminal 121 in a terminal portion can be formed to have a single-layer structure or a stacked-layer structure using any of the conductive materials described in Embodiment 1.

Next, the gate insulating layer 102 is formed over the entire area over the gate electrode layer 101. The gate insulating layer 102 is formed by a CVD method, a sputtering method, or the like to a thickness of 50 nm to 250 nm.

For example, the gate insulating layer 102 is formed using a silicon oxide film with a thickness of 100 nm by a CVD method or a sputtering method. Needless to say, the gate insulating layer 102 is not limited to such a silicon oxide film. The gate insulating layer 102 may be formed to have a single-layer structure or a stacked-layer structure using another insulating film such as a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, or a tantalum oxide film.

Alternatively, the gate insulating layer 102 can be formed of a silicon oxide layer by a CVD method using an organosilane gas. As the organosilane gas, a silicon-containing compound such as tetraethoxysilane (TEOS: chemical formula, Si(OC₂H₅)₄), tetramethylsilane (TMS: chemical formula, Si(CH₃)₄), tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC₂H₅)₃), or trisdimethylaminosilane (SiH(N(CH₃)₂)₃) can be used.

Further alternatively, the gate insulating layer 102 may be formed using one kind of oxide, nitride, oxynitride, or nitride oxide of aluminum, yttrium, or hafnium; or a compound including at least two or more kinds of the aforementioned compounds.

Note that in this specification, oxynitride refers to a substance that contains more oxygen atoms than nitrogen atoms and nitride oxide refers to a substance that contains more nitrogen atoms than oxygen atoms. For example, a “silicon oxynitride film” means a film that contains more oxygen atoms than nitrogen atoms, and oxygen, nitrogen, silicon, and hydrogen at concentrations ranging from 50 atomic % to 70 atomic %, 0.5 atomic % to 15 atomic %, 25 atomic % to 35 atomic %, and 0.1 atomic % to 10 atomic %, respectively, when they are measured by RBS (Rutherford Backscattering Spectrometry) and HFS (Hydrogen Forward Scattering). Further, a “silicon nitride oxide film” means a film that contains more nitrogen atoms than oxygen atoms, and oxygen, nitrogen, silicon, and hydrogen at concentrations ranging from 5 atomic % to 30 atomic %, 20 atomic % to 55 atomic %, atomic % to 35 atomic %, and 10 atomic % to 30 atomic %, respectively, when they are measured by RBS and HFS. Note that percentages of nitrogen, oxygen, silicon, and hydrogen fall within the ranges given above, where the total number of atoms contained in the silicon oxynitride or the silicon nitride oxide is defined as 100 atomic %.

Next, a second photolithography step is performed. A resist mask is formed over the gate insulating layer 102, and an unnecessary portion is removed by etching, whereby a contact hole reaching the wiring or the electrode layer which is formed using the same material as the gate electrode layer 101 is formed in the gate insulating layer 102. This contact hole is provided for direct contact with a conductive film formed later. For example, a contact hole is formed when a terminal that is electrically connected to the first terminal 121 in the terminal portion is formed.

Next, a first conductive film 112, a second conductive film 113, and a third conductive film 114 are formed over the gate insulating layer 102 by a sputtering method or a vacuum evaporation method with use of a metal material. A cross-sectional view at this stage is illustrated in FIG. 2B.

The first conductive film 112, the second conductive film 113, and the third conductive film 114 can be formed to have a single-layer structure or a stacked-layer structure using any of the conductive materials described in Embodiment 1. In this embodiment, the first conductive film 112 and the third conductive film 114 are formed using titanium that is a heat-resistant conductive material, and the second conductive film 113 is formed using an aluminum alloy containing neodymium. By such a structure, a low resistance property of aluminum is utilized and generation of a hillock can be reduced.

Next, a third photolithography step is performed. A resist mask 131 is formed, and an unnecessary portion is removed by etching, whereby the source and drain electrode layers 105 a and 105 b and a connection electrode 120 are formed. Wet etching or dry etching is used as an etching method at this time. For example, in the case where the first conductive film 112 and the third conductive film 114 are formed using titanium and the second conductive film 113 is formed using an aluminum alloy containing neodymium, wet etching can be performed by using a hydrogen peroxide solution, heated hydrochloric acid, or a nitric acid aqueous solution containing ammonium fluoride as etchant. For example, the first conductive film 112, the second conductive film 113, and the third conductive film 114 can be etched in one step with use of KSMF-240 (manufactured by KANTO CHEMICAL CO., INC.).

Further, the first conductive film 112, the second conductive film 113, and the third conductive film 114 can be etched in one step by etching in which a hydrogen peroxide solution, heated hydrochloric acid, or a nitric acid aqueous solution containing ammonium fluoride is used as etchant; therefore, end portions of the conductive films included in the source and drain electrode layers 105 a and 105 b are aligned with each other, and a continuous structure can be formed. The source and drain electrode layers 105 a and 105 b are etched to have a tapered edge, whereby coverage with the first oxide semiconductor region 103 can be improved and disconnection of the first oxide semiconductor region 103 due to a step shape can be prevented. A cross-sectional view at this stage is illustrated in FIG. 2C. Note that a plan view at this stage corresponds to FIG. 5.

In the third photolithography step, a second terminal 122 made from the same material as the source and drain electrode layers 105 a and 105 b is also left in the terminal portion. Note that the second terminal 122 is electrically connected to a source wiring (a source wiring including the source and drain electrode layers 105 a and 105 b).

In the terminal portion, the connection electrode 120 is directly connected to the first terminal 121 through the contact hole formed in the gate insulating layer 102.

Next, the gate insulating layer 102 and the source and drain electrode layers 105 a and 105 b are subjected to surface treatment. As the surface treatment, for example, plasma treatment in which an inert gas or a reactive gas is used can be performed.

After the resist mask 131 is removed, reverse sputtering by which plasma is generated by introducing an argon gas into a chamber in which the substrate 100 is disposed is performed, whereby impurities attached to a surface of the gate insulating layer 102 are removed. In addition, by performing the reverse sputtering, planarity of the surface of the gate insulating layer 102 can be improved. A cross-sectional view at this stage is illustrated in FIG. 2D. The reverse sputtering refers to a method in which, without application of voltage to a target side, an RF power source is used for application of voltage to a substrate side in an argon atmosphere to modify a surface. Note that instead of an argon atmosphere, a nitrogen atmosphere, a helium atmosphere, or the like may be used. Alternatively, an argon atmosphere to which oxygen, hydrogen, N₂O, or the like is added may be used. Further alternatively, an argon atmosphere to which Cl₂, CF₄, or the like is added may be used. After the reverse sputtering, a first oxide semiconductor film is formed without being exposed to air, whereby dust or moisture can be prevented from attaching to an interface between the gate insulating layer 102 and the first oxide semiconductor region 103.

Next, oxide semiconductor films for forming the first oxide semiconductor region 103 and the second oxide semiconductor region 104 are formed. In this embodiment, the first oxide semiconductor region 103 and the second oxide semiconductor region 104 are formed using different oxide semiconductor layers. First, over the gate insulating layer 102, the first oxide semiconductor film for forming the first oxide semiconductor region 103 is formed by a sputtering method in an atmosphere of an oxygen gas and a rare gas such as argon. As the first oxide semiconductor film, the oxide semiconductor described in Embodiment 1 can be used, and an In—Ga—Zn—O-based oxide semiconductor is preferably used. A specific example of conditions for forming the first oxide semiconductor film is as follows: An oxide semiconductor target containing In, Ga, and Zn (In₂O₃:Ga₂O₃:ZnO=1:1:1) of 8 inches in diameter is used, the distance between the substrate and the target is set to 170 mm, a flow rate ratio of Ar to O₂ is 50 to 5 (sccm), and film formation is performed by sputtering at a pressure of 0.4 Pa, with a direct-current (DC) power source of 0.5 kW, and at room temperature. Further, as the target, Ga₂O₃ and ZnO in a pellet state may be disposed on a disk of 8 inches in diameter which contains In₂O₃. Further, a pulsed direct current (DC) power source is preferably used because dust can be reduced and a thickness distribution can be uniform. The thickness of the first oxide semiconductor film is set to 10 nm to 300 nm, preferably, 20 nm to 100 nm.

Next, a second oxide semiconductor film for forming the second oxide semiconductor region 104 is formed by a sputtering method without being exposed to air in an atmosphere of an oxygen gas and a rare gas such as argon. As the second oxide semiconductor film, the oxide semiconductor described in Embodiment 1 can be used, and an In—Ga—Zn—O-based oxide semiconductor is preferably used. After the first oxide semiconductor film is formed, the second oxide semiconductor film is formed without being exposed to air, whereby dust or moisture can be prevented from attaching to an interface between the first oxide semiconductor region 103 and the second oxide semiconductor region 104, and change in the film quality or the composition of the first oxide semiconductor region 103 can be prevented. A specific example of conditions for forming the second oxide semiconductor film is as follows: An oxide semiconductor target containing In, Ga, and Zn (In₂O₃:Ga₂O₃:ZnO=1:1:1) of 8 inches in diameter is used, the distance between the substrate and the target is set to 170 mm, a flow rate ratio of Ar to O₂ is 50 to 1 (sccm), and film formation is performed by sputtering at a pressure of 0.4 Pa, with a direct-current (DC) power source of 0.5 kW, and at room temperature. Further, as the target, Ga₂O₃ and ZnO in a pellet state may be disposed on a disk of 8 inches in diameter which contains In₂O₃. Note that a pulsed direct current (DC) power source is preferably used because dust can be reduced and a thickness distribution can be uniform. The thickness of the second oxide semiconductor film is set to 5 nm to 1000 nm, preferably, 10 nm to 100 nm.

Here, the proportion of the flow rate of the oxygen gas in the whole film-forming gas for forming the second oxide semiconductor film by sputtering is made higher than that of the oxygen gas in the whole film-forming gas for forming the first oxide semiconductor film by sputtering. Accordingly, the electrical conductivity of the thus-formed second oxide semiconductor film can be lower than that of the thus-formed first oxide semiconductor film. Further, the proportion of the flow rate of the oxygen gas in the whole film-forming gas for forming the second oxide semiconductor film is preferably 70 volume % or higher. The proportion of the flow rate of the oxygen gas in the whole film-forming gas for forming the first oxide semiconductor film is preferably lower than 70 volume %.

Note that, in this embodiment, the first oxide semiconductor region 103 and the second oxide semiconductor region 104 are formed using different oxide semiconductor films; however, the present invention is not limited thereto. The first oxide semiconductor film for forming the first oxide semiconductor region 103 and the second oxide semiconductor film for forming the second oxide semiconductor region 104 are formed in one step by continuously increasing the flow rate of the oxygen gas, whereby the first oxide semiconductor film and the second oxide semiconductor film can be formed as the same oxide semiconductor film whose electrical conductivity is continuously changed. Alternatively, formation of an oxide semiconductor film is performed plural times by gradually increasing the flow rate of the oxygen gas, whereby a plurality of oxide semiconductor films whose electrical conductivity is gradually changed can be formed between the first oxide semiconductor film for forming the first oxide semiconductor region 103 and the second oxide semiconductor film for forming the second oxide semiconductor region 104.

Further, the first oxide semiconductor film and the second oxide semiconductor film can be successively formed, whereby efficiency in manufacturing a display device and productivity can be improved.

A chamber used for forming the first oxide semiconductor film and the second oxide semiconductor film may be the same or different from the chamber in which the reverse sputtering has been performed.

Examples of a sputtering method include an RF sputtering method in which a high-frequency power source is used for a sputtering power source, a DC sputtering method, and a pulsed DC sputtering method in which a bias is applied in a pulsed manner. An RF sputtering method is mainly used in the case of forming an insulating film, and a DC sputtering method is mainly used in the case of forming a metal film.

In addition, there is also a multi-source sputtering apparatus in which a plurality of targets of different materials can be set. With the multi-source sputtering apparatus, films of different materials can be formed to be stacked in the same chamber, or a plurality of kinds of materials can be formed by electric discharge at the same time in the same chamber.

In addition, there are a sputtering apparatus provided with a magnet system inside the chamber and used for a magnetron sputtering method, or a sputtering apparatus used for an ECR sputtering method in which plasma generated with the use of microwaves is used without using glow discharge.

In addition, as a film formation method by sputtering, there are also a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted with each other during film formation to form a thin compound film thereof, and a bias sputtering method in which voltage is also applied to a substrate during film formation.

Next, a fourth photolithography step is performed. A resist mask is formed, and the first oxide semiconductor film and the second oxide semiconductor film are etched. Here, the resist mask is formed over the second oxide semiconductor film, whereby the resist mask can be prevented from being in direct contact with the first oxide semiconductor film, and impurities can be prevented form entering the first oxide semiconductor film from the resist mask. In the case of using O₂ ashing or a resist stripper for removal of the resist, the second oxide semiconductor film is formed over the first oxide semiconductor film; thus, contamination of the first oxide semiconductor film can be prevented.

An unnecessary portion is removed by the etching. Thus, the first oxide semiconductor film and the second oxide semiconductor film are processed into an island shape, whereby the first oxide semiconductor region 103 formed from the first oxide semiconductor film and the second oxide semiconductor region 104 formed from the second oxide semiconductor film are formed. The etching of the first oxide semiconductor film and the second oxide semiconductor film can be performed by wet etching in which organic acid such as citric acid or oxalic acid is used for etchant. For example, in the case where an In—Ga—Zn—O-based non-single-crystal film is used as the first oxide semiconductor film and the second oxide semiconductor film, ITO-07N (manufactured by KANTO CHEMICAL CO., INC.) is preferably used.

Note that etching here is not limited to wet etching and may be dry etching. As an etching apparatus used for the dry etching, an etching apparatus using a reactive ion etching method (an RIE method), or a dry etching apparatus using a high-density plasma source such as ECR (electron cyclotron resonance) or ICP (inductively coupled plasma) can be used. As a dry etching apparatus by which uniform discharge can be obtained over a wider area as compared to an ICP etching apparatus, there is an ECCP (enhanced capacitively coupled plasma) mode apparatus in which an upper electrode is grounded, a high-frequency power source at 13.56 MHz is connected to a lower electrode, and further a low-frequency power source at 3.2 MHz is connected to the lower electrode. This ECCP mode etching apparatus can be applied even when, as the substrate, a substrate, the size of which exceeds 3 m of the tenth generation, is used, for example. Through the above steps, a thin film transistor 170 in which the first oxide semiconductor region 103 serves as a channel formation region can be manufactured. A cross-sectional view at this stage is illustrated in FIG. 3A. Note that a top view at this stage corresponds to FIG. 6.

In the thin film transistor 170, the first oxide semiconductor region 103 serves as an active layer. On the other hand, the second oxide semiconductor region 104 having lower electrical conductivity than the first oxide semiconductor region 103 serves as a protective layer for preventing the first oxide semiconductor region 103 from being exposed to air and from being in contact with a film containing impurities which change composition or film quality of an oxide semiconductor. At this time, the first oxide semiconductor region 103 which includes a channel formation region and determines the electrical characteristics of the thin film transistor is in contact with the second oxide semiconductor region 104 whose composition and film quality are similar to those of the first oxide semiconductor region 103, whereby change in the composition, the film quality, the interface, or the like of the first oxide semiconductor region 103 due to impurities can be prevented. Although the second oxide semiconductor region 104 serving as a protective layer is in contact with a film containing impurities which change composition or film quality of an oxide semiconductor, the second oxide semiconductor region 104 has lower conductivity than the first oxide semiconductor region 103. Thus, the electrical characteristics of the thin film transistor are not affected.

After the resist mask is removed, heat treatment at 200° C. to 600° C., typically 250° C. to 500° C., is preferably performed. Here, heat treatment is performed in a nitrogen atmosphere in a furnace at 350° C. for one hour. Through this heat treatment, rearrangement at the atomic level occurs in the In—Ga—Zn—O-based non-single-crystal film. Because strain energy which inhibits carrier movement is released by the heat treatment, the heat treatment (including optical annealing) is important. Note that there is no particular limitation on the timing of heat treatment as long as it is performed after formation of the second In—Ga—Zn—O-based non-single-crystal film, and for example, heat treatment may be performed after formation of a pixel electrode.

Next, a protective insulating layer 107 is formed to cover the thin film transistor 170. For the protective insulating layer 107, a silicon nitride film, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, a tantalum oxide film, or the like which is obtained by a sputtering method or the like can be used.

Next, a fifth photolithography step is performed. A resist mask is formed, and the protective insulating layer 107 is etched to form a contact hole 125 reaching the source or drain electrode layer 105 b. In addition, by the etching here, a contact hole 127 which reaches the second terminal 122 and a contact hole 126 which reaches the connection electrode 120 are formed. A cross-sectional view at this stage is illustrated in FIG. 3B.

Then, after the resist mask is removed, a transparent conductive film is formed. The transparent conductive film is formed using indium oxide (In₂O₃), an alloy of indium oxide and tin oxide (In₂O₃—SaO₂, abbreviated as ITO), or the like by a sputtering method, a vacuum evaporation method, or the like. Etching treatment of such a material is performed with a hydrochloric acid based solution. Instead, because a residue tends to be generated particularly in etching of ITO, an alloy of indium oxide and zinc oxide (In₂O₃—ZnO) may be used in order to improve etching processability.

Next, a sixth photolithography step is performed. A resist mask is formed, and an unnecessary portion is removed by etching to form a pixel electrode layer 110. The pixel electrode layer 110 is directly connected to the source or drain electrode layer 105 b through the contact hole 125.

In the sixth photolithography step, a storage capacitor is formed with the capacitor wiring 108 and the pixel electrode layer 110, in which the gate insulating layer 102 and the protective insulating layer 107 in the capacitor portion are used as a dielectric.

In addition, in the sixth photolithography step, the first terminal and the second terminal are covered with the resist mask, and transparent conductive films 128 and 129 are left in the terminal portion. The transparent conductive films 128 and 129 serve as electrodes or wirings that are used for connection with an FPC. The transparent conductive film 128 formed over the connection electrode 120 that is directly connected to the first terminal 121 serves as a connection terminal electrode which functions as an input terminal for the gate wiring. The transparent conductive film 129 formed over the second terminal 122 serves as a connection terminal electrode which functions as an input terminal for the source wiring.

Then, the resist mask is removed. A cross-sectional view at this stage is illustrated in FIG. 3C. Note that a plan view at this stage corresponds to FIG. 7.

Further, FIGS. 8A-1 and 8A-2 are a cross-sectional view of a gate wiring terminal portion at this stage and a plan view thereof, respectively. FIGS. 8A-1 is a cross-sectional view taken along line C1-C2 of FIGS. 8A-2. In FIGS. 8A-1, a transparent conductive film 155 formed over a protective insulating film 154 is a connection terminal electrode serving as an input terminal. Furthermore, in FIGS. 8A-1, in the terminal portion, the first terminal 151 formed from the same material as the gate wiring and a connection electrode 153 formed from the same material as the source wiring are overlapped with each other with a gate insulating layer 152 interposed therebetween and are electrically connected. In addition, the connection electrode 153 and the transparent conductive film 155 are in direct contact with each other through a contact hole provided in the protective insulating film 154 to form conduction therebetween.

Further, FIGS. 8B-1 and 8B-2 are a cross-sectional view of a source wiring terminal portion and a plan view thereof, respectively. FIGS. 8B-1 is a cross-sectional view taken along line D1-D2 of FIGS. 8B-2. In FIGS. 8B-1, the transparent conductive film 155 formed over the protective insulating film 154 is a connection terminal electrode serving as an input terminal. Furthermore, in FIGS. 8B-1, in the terminal portion, an electrode 156 formed from the same material as the gate wiring is located below and overlapped with the second terminal 150, which is electrically connected to the source wiring, with the gate insulating layer 152 interposed therebetween. The electrode 156 is not electrically connected to the second terminal 150. When the electrode 156 is set to, for example, floating, GND, or 0 V such that the potential of the electrode 156 is different from the potential of the second terminal 150, a capacitor for preventing noise or static electricity can be formed. In addition, the second terminal 150 is electrically connected to the transparent conductive film 155 with the protective insulating film 154 interposed therebetween.

A plurality of gate wirings, source wirings, and capacitor wirings are provided depending on the pixel density. Also in the terminal portion, the first terminal at the same potential as the gate wiring, the second terminal at the same potential as the source wiring, the third terminal at the same potential as the capacitor wiring, and the like are each arranged in plurality. There is no particular limitation on the number of each of the terminals, and the number of the terminals may be determined by a practitioner as appropriate.

By these six photolithography steps, using six photomasks, a pixel thin film transistor portion including the thin film transistor 170 that is a bottom-gate n-channel thin film transistor, and a storage capacitor can be completed. These are arranged in matrix in respective pixels so that a pixel portion is formed, which can be used as one of substrates for manufacturing an active matrix display device. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

When an active matrix liquid crystal display device is manufactured, an active matrix substrate and a counter substrate provided with a counter electrode are bonded to each other with a liquid crystal layer interposed therebetween. Note that a common electrode electrically connected to the counter electrode on the counter substrate is provided over the active matrix substrate, and a fourth terminal electrically connected to the common electrode is provided in the terminal portion. This fourth terminal is provided so that the common electrode is fixed to a predetermined potential such as GND or 0 V.

Further, this embodiment is not limited to a pixel structure in FIG. 7, and an example of a pixel structure different from the pixel structure in FIG. 7 is illustrated in FIG. 9. FIG. 9 illustrates an example in which a capacitor wiring is not provided and a storage capacitor is formed with a pixel electrode and a gate wiring of an adjacent pixel which overlap each other with a protective insulating film and a gate insulating layer interposed therebetween. In this case, the capacitor wiring and the third terminal connected to the capacitor wiring can be omitted. Note that in FIG. 9, the same portions as those in FIG. 7 are denoted by the same reference numerals.

In an active matrix liquid crystal display device, display patterns are formed on a screen by driving of pixel electrodes that are arranged in matrix. Specifically, voltage is applied between a selected pixel electrode and a counter electrode corresponding to the pixel electrode, and thus, a liquid crystal layer disposed between the pixel electrode and the counter electrode is optically modulated. This optical modulation is recognized as a display pattern by a viewer.

A liquid crystal display device has a problem in that, when displaying a moving image, image sticking occurs or the moving image is blurred because the response speed of liquid crystal molecules themselves is low. As a technique for improving moving image characteristics of a liquid crystal display device, there is a driving technique which is so-called black insertion by which an entirely black image is displayed every other frame.

Further, there is another driving technique which is so-called double-frame rate driving. In the double-frame rate driving, a vertical synchronizing frequency is set 1.5 times or more, preferably 2 times or more as high as a usual vertical synchronizing frequency, whereby moving image characteristics are improved.

Furthermore, as a technique for improving moving image characteristics of a liquid crystal display device, there is another driving technique in which, as a backlight, a surface light source including a plurality of LED (light-emitting diode) light sources or a plurality of EL light sources is used, and each light source included in the surface light source is independently driven so as to perform intermittent lightning in one frame period. As the surface light source, three or more kinds of LEDs may be used, or a white-light-emitting LED may be used. Since a plurality of LEDs can be controlled independently, the timing at which the LEDs emit light can be synchronized with the timing at which optical modulation of a liquid crystal layer is switched. In this driving technique, part of LEDs can be turned off. Therefore, especially in the case of displaying an image in which the proportion of a black image area in one screen is high, a liquid crystal display device can be driven with low power consumption.

When combined with any of these driving techniques, a liquid crystal display device can have better display characteristics such as moving image characteristics than conventional liquid crystal display devices.

The n-channel thin film transistor obtained in this embodiment uses an oxide semiconductor for a channel formation region and has excellent dynamic characteristics; thus, it can be combined with these driving techniques. More preferably, an In—Ga—Zn—O-based non-single-crystal film is used for a channel formation region.

In the case of manufacturing a light-emitting display device, one electrode (also called a cathode) of an organic light-emitting element is set at a low power supply potential such as GND or 0 V; thus, a fourth terminal for setting the cathode at a low power supply potential such as GND or 0 V is provided in a terminal portion. In addition, in the case of manufacturing a light-emitting display device, besides a source wiring and a gate wiring, a power supply line is provided. Accordingly, a fifth terminal which is electrically connected to the power supply line is provided in a terminal portion.

As described above, between a first oxide semiconductor region serving as an active layer and a protective insulating layer for a thin film transistor, a second oxide semiconductor region having lower electrical conductivity than the first oxide semiconductor region and serving as a protective layer is formed. Accordingly, change in composition or deterioration in film quality of the first oxide semiconductor region can be prevented, and electrical characteristics of the thin film transistor can be stabilized.

By using the thin film transistor for a pixel portion and a driver circuit portion of the display device, a display device with high electrical characteristics and high reliability can be provided.

Note that the structure described in this embodiment can be combined with any of the structures described in another embodiment as appropriate.

Embodiment 3

In this embodiment, a thin film transistor having a different structure than that of the thin film transistor described in Embodiment 1 is described with reference to FIG. 10.

A thin film transistor having a bottom gate structure of this embodiment is illustrated in FIG. 10. In the thin film transistor illustrated in FIG. 10, the gate electrode layer 101 is provided over the substrate 100, the gate insulating layer 102 is provided over the gate electrode layer 101, the source and drain electrode layers 105 a and 105 b are provided over the gate insulating layer 102, buffer layers 301 a and 301 b are provided over the source and drain electrode layers 105 a and 105 b, the first oxide semiconductor region 103 is provided over the gate insulating layer 102 and the buffer layers 301 a and 301 b, and the second oxide semiconductor region 104 having lower electrical conductivity than the first oxide semiconductor region 103 is provided over the first oxide semiconductor region 103. Note that the first oxide semiconductor region 103 and the second oxide semiconductor region 104 may be formed in the same oxide semiconductor layer, or may be formed as different oxide semiconductor layers. Further, between the first oxide semiconductor region 103 and the second oxide semiconductor region 104, an intermediate region between oxide semiconductors, whose electrical conductivity is gradually or continuously changed, may be present. The intermediate region between the oxide semiconductors may be formed in the oxide semiconductor layer in which the first oxide semiconductor region 103 and the second oxide semiconductor region 104 are formed, or may be formed as an oxide semiconductor layer which is different from the first oxide semiconductor region 103 and the second oxide semiconductor region 104.

The source or drain electrode layer 105 a has a three-layer structure of the first conductive film 112 a, the second conductive film 113 a, and the third conductive film 114 a while the source or drain electrode layer 105 b has a three-layer structure of the first conductive film 112 b, the second conductive film 113 b, and the third conductive film 114 b. That is, the thin film transistor illustrated in FIG. 10 has a structure in which the buffer layers 301 a and 301 b are provided between the first oxide semiconductor region 103 and the source and drain electrode layers 105 a and 105 b in the thin film transistor illustrated in FIGS. 1A and 1B in Embodiment 1.

The buffer layers 301 a and 301 b serving as a source and drain regions can be formed using an oxide semiconductor for forming the first oxide semiconductor region 103 and the second oxide semiconductor region 104, which is described in Embodiment 1. In a manner similar to formation of the first oxide semiconductor region 103 and the second oxide semiconductor region 104, the buffer layers are preferably formed using an In—Ga—Zn—O-based non-single-crystal film which is an oxide semiconductor film containing In, Ga, and Zn. Note that the buffer layers 301 a and 301 b have n-type conductivity, and the electrical conductivity of the buffer layers 301 a and 301 b is made higher than that of the first oxide semiconductor region 103 and that of the second oxide semiconductor region 104. For example, the electrical conductivity of the buffer layers 301 a and 301 b is preferably higher than 1.0×10⁻³ S/cm. In the case where an In—Ga—Zn—O-based non-single-crystal film is used as the buffer layers 301 a and 301 b, at least an amorphous component is included in the In—Ga—Zn—O-based non-single-crystal film, and crystal grains (nanocrystals) are included in the amorphous structure of the buffer layers 301 a and 301 b in some cases. The crystal grains (nanocrystals) each have a diameter of 1 nm to 10 nm, typically, about 2 nm to 4 nm.

The oxide semiconductor film used for the buffer layers 301 a and 301 b is formed by a sputtering method. A specific example of conditions for forming the oxide semiconductor film is as follows: An oxide semiconductor target containing In, Ga, and Zn (In₂O₃:Ga₂O₃:ZnO=1:1:1) of 8 inches in diameter is used, the distance between the substrate and the target is set to 170 mm, a flow rate ratio of Ar to O₂ is 50 to 1 (sccm), and film formation is performed by sputtering at a pressure of 0.4 Pa, with a direct-current (DC) power source of 0.5 kW, and at room temperature. Note that the presence or absence of the crystal grains or the density of the crystal grains can be adjusted and the diameter size can be adjusted by appropriate adjustment of the composition ratio in the target, the film forming pressure (0.1 Pa to 2.0 Pa), the power (250 W to 3000 W: 8 inches ø), the temperature (room temperature to 100° C.), the reactive sputtering film formation conditions, or the like.

Note that the conditions for forming the oxide semiconductor film used for the buffer layers 301 a and 301 b are different from those for forming the oxide semiconductor film used for the first oxide semiconductor region 103 and the second oxide semiconductor region 104. The proportion of the flow rate of an oxygen gas in the film-forming gas for forming the oxide semiconductor film used for the buffer layers 301 a and 301 b is made lower than that of the oxygen gas in the film-forming gas for forming the oxide semiconductor film used for the first oxide semiconductor region 103 and the second oxide semiconductor region 104. For example, the proportion of the flow rate of the oxygen gas in the whole film-forming gas for forming the oxide semiconductor film used for the buffer layers 301 a and 301 b is preferably lower than 10 volume %. The oxide semiconductor film used for the buffer layers 301 a and 301 b may be formed in an atmosphere of a rare gas such as an argon gas without containing an oxygen gas.

The thickness of the oxide semiconductor film used for the buffer layers 301 a and 301 b is set to 5 nm to 20 nm. Needless to say, when the film includes crystal grains, the size of the crystal grains does not exceed the thickness of the film. In this embodiment, the thickness of the oxide semiconductor film used for the buffer layers 301 a and 301 b is set to 5 nm.

The buffer layers 301 a and 301 b may contain an impurity element imparting n-type conductivity. As an example of the impurity element, it is possible to use, for example, magnesium, aluminum, titanium, iron, tin, calcium, germanium, scandium, yttrium, zirconium, hafnium, boron, thallium, or lead. In the case where magnesium, aluminum, titanium, or the like is contained in the buffer layers, there is an effect of blocking oxygen, and the like, so that the oxygen concentration of an oxide semiconductor layer can be maintained within an optimal range by heat treatment or the like after film formation.

The carrier concentration of the buffer layers is preferably 1×10¹⁸/cm³ or higher (and 1×10²²/cm³ or lower).

As described above, provision of the buffer layers 301 a and 301 b can make thermal stability improved more than formation of Schottky junction do, between the first oxide semiconductor region 103 and the source and drain electrode layers 105 a and 105 b, whereby operating characteristics of the thin film transistor can be stabilized. In addition, because of high electrical conductivity, favorable mobility can be ensured even when high drain voltage is applied.

Note that, as for a structure and materials of the thin film transistor of this embodiment other than the buffer layers 301 a and 301 b, Embodiment 1 is to be referred to.

A manufacturing process of the thin film transistor of this embodiment is almost similar to the manufacturing process of the thin film transistor described in Embodiment 2. First, by the method described in Embodiment 2, steps up to forming the first conductive film 112, the second conductive film 113, and the third conductive film 114 are performed. Following the above steps, an oxide semiconductor film 302 for forming the buffer layers 301 a and 301 b is formed by sputtering with use of the above method (see FIG. 11A). Next, by a third photolithography step, the oxide semiconductor film 302 is etched into an island shape at the same time as etching of the first conductive film 112, the second conductive film 113, and the third conductive film 114, whereby the source and drain electrode layers 105 a and 105 b and oxide semiconductor films 302 a and 302 b are formed. Then, by the method described in Embodiment 2, reverse sputtering is performed (see FIG. 11B). Next, by the method described in Embodiment 2, the oxide semiconductor films 302 a and 302 b are etched at the same time as forming the first oxide semiconductor region 103 and the second oxide semiconductor region 104, whereby the buffer layers 301 a and 301 b are formed (see FIG. 11C). Subsequent steps are similar to those in Embodiment 2.

Note that the structure described in this embodiment can be combined with any of the structures described in another embodiment as appropriate.

Embodiment 4

In this embodiment, a thin film transistor having a different structure than those of the thin film transistors described in Embodiments 1 and 3 is described with reference to FIGS. 30A and 30B.

Thin film transistors each having a bottom gate structure of this embodiment are illustrated in FIGS. 30A and 30B. In each of the thin film transistors illustrated in FIGS. 30A and 30B, the gate electrode layer 101 is provided over the substrate 100, the gate insulating layer 102 is provided over the gate electrode layer 101, the source and drain electrode layers 105 a and 105 b are provided over the gate insulating layer 102, the first oxide semiconductor region 103 is provided over the gate insulating layer 102 and the source and drain electrode layers 105 a and 105 b, and the second oxide semiconductor region 104 having lower electrical conductivity than the first oxide semiconductor region 103 is provided over the first oxide semiconductor region 103. Note that the first oxide semiconductor region 103 and the second oxide semiconductor region 104 may be formed in the same oxide semiconductor layer, or may be formed as different oxide semiconductor layers. Further, between the first oxide semiconductor region 103 and the second oxide semiconductor region 104, the intermediate region between the oxide semiconductors, whose electrical conductivity is gradually or continuously changed, may be present. The intermediate region between the oxide semiconductors may be formed in the oxide semiconductor layer in which the first oxide semiconductor region 103 and the second oxide semiconductor region 104 are formed, or may be formed as an oxide semiconductor layer which is different from the first oxide semiconductor region 103 and the second oxide semiconductor region 104.

The source or drain electrode layer 105 a has a three-layer structure of the first conductive film 112 a, the second conductive film 113 a, and the third conductive film 114 a while the source or drain electrode layer 105 b has a three-layer structure of a first conductive film 112 b, a second conductive film 113 b, and a third conductive film 114 b. Insulating layers are provided on side surfaces of the source and drain electrode layers 105 a and 105 b. In FIG. 30A, oxide films 403 a and 403 b are formed on the side surfaces of the source and drain electrode layers 105 a and 105 b, respectively. In FIG. 30B, sidewall insulating layers 404 a and 404 b are formed on the side surfaces of the source and drain electrode layers 105 a and 105 b.

That is, the thin film transistor illustrated in FIG. 30A has a structure in which the first oxide semiconductor region 103 in the thin film transistor illustrated in FIGS. 1A and 1B in Embodiment 1 is partly in contact with the side surface portions of the source and drain electrode layer 105 a and 105 b through the oxide films 403 a and 403 b. The thin film transistor illustrated in FIG. 30B has a structure in which the first oxide semiconductor region 103 in the thin film transistor illustrated in FIGS. 1A and 1B in Embodiment 1 is partly in contact with the side surface portions of the source and drain electrode layers 105 a and 105 b through the sidewall insulating layers 404 a and 404 b.

The oxide films 403 a and 403 b illustrated in FIG. 30A are formed by oxidizing the side surfaces of the source and drain electrode layers 105 a and 105 b. As an oxidation method, thermal oxidation, oxygen plasma treatment, cleaning with ozone water, or the like is preferably performed. Specifically, by performing thermal oxidation, plasma oxidation, or ozone water treatment in a state where the source and drain electrode layers 105 a and 105 b illustrated in FIG. 2C in Embodiment 2 are formed and the resist mask 131 is left, the side surfaces of the source and drain electrode layers 105 a and 105 b are preferably oxidized to form the oxide films 403 a and 403 b. Note that, in the case where the source and drain electrode layers 105 a and 105 b each have a stacked structure of different conductive films, the oxide films 403 a and 403 also each have a stacked structure of different oxide films. For example, in the case where the first conductive films 112 a and 112 b and the third conductive films 114 a and 114 b are formed using titanium and the second conductive films 113 a and 113 b are formed using an aluminum alloy containing neodymium, the oxide films 403 a and 403 b each have a three-layer structure in which a titanium oxide film, an aluminum oxide alloy film containing neodymium, and a titanium oxide film are formed in this order from the upper side. Note that the electrical conductivity of the oxide films 403 a and 403 b is lower than that of the first oxide semiconductor region 103.

The sidewall insulating layers 404 a and 404 b illustrated in FIG. 30B are formed using a silicon film, a silicon oxide film, a silicon nitride oxide film, or a silicon oxynitride film. Specifically, after the source and drain electrode layers 105 a and 105 b illustrated in FIG. 2C in Embodiment 2 are formed and the resist mask 131 is removed by a plasma CVD method, a sputtering method, or the like, a silicon film, a silicon oxide film, a silicon nitride oxide film, or a silicon oxynitride film is formed so as to cover the source and drain electrode layers 105 a and 105 b. Next, anisotropic etching mainly in a perpendicular direction is performed, whereby the newly formed silicon film, silicon oxide film, silicon nitride oxide film, or silicon oxynitride film is partly etched, and the sidewall insulating layers 404 a and 404 b in contact with the side surfaces of the source and drain electrode layers 105 a and 105 b can be formed. Dry etching is preferably employed as the anisotropic etching at this time, and a mixed gas of CHF₃ and helium can be used as an etching gas. Note that, in the case where the same kind of silicon film as that of the gate insulating layer is used as the sidewall insulating layers, etching selectivity cannot be achieved. Therefore, by the above anisotropic etching, the gate insulating layer 102 is also etched in some cases.

As illustrated in FIGS. 30A and 30B, by providing the oxide films 403 a and 403 b or the sidewall insulating layers 404 a and 404 b on the side surfaces of the source and drain electrode layers 105 a and 105 b, drain current can flow not through a linear path connecting the source and drain electrode layers 105 a and 105 b, but through a path making a detour through the oxide films 403 a and 403 b or the sidewall insulating layers 404 a and 404 b. Accordingly, off current which flows when the thin film transistor is turned off can be reduced. Without being limited to the thin film transistor having the structure in which the second oxide semiconductor region 104 is provided, a thin film transistor having a structure in which the second oxide semiconductor region 104 is not provided and an active layer is a single oxide semiconductor layer can also obtain a similar effect by providing the oxide films 403 a and 403 b or the sidewall insulating layers 404 a and 404 b on the side surfaces of the source and drain electrode layers 105 a and 105 b.

By providing the oxide films 403 a and 403 b or the sidewall insulating layers 404 a and 404 b on the side surfaces of the source and drain electrode layers 105 a and 105 b, coverage with the first oxide semiconductor region 103 can be improved and disconnection of the first oxide semiconductor region 103 due to a step shape can be prevented.

Note that, buffer layers may be provided between the first oxide semiconductor region 103 and the source and drain electrode layers 105 a and 105 b also in this embodiment, as described in Embodiment 3.

Note that, as for a structure and materials of the thin film transistor of this embodiment other than the oxide films 403 a and 403 b and the sidewall insulating layers 404 a and 404 b, Embodiment 1 is to be referred to.

Note that the structure described in this embodiment can be combined with any of the structures described in another embodiment as appropriate.

Embodiment 5

In this embodiment, an example will be described below, in which at least part of a driver circuit and a thin film transistor arranged in a pixel portion are formed over the same substrate in a display device which is one example of a semiconductor device.

The thin film transistor to be arranged in the pixel portion is formed according to any of Embodiments 1 to 4. Further, the thin film transistor described in any of Embodiments 1 to 4 is an n-channel TFT, and thus part of a driver circuit that can include an n-channel TFT among driver circuits is formed over the same substrate as the thin film transistor of the pixel portion.

FIG. 14A illustrates an example of a block diagram of an active matrix liquid crystal display device which is an example of a semiconductor device. The display device illustrated in FIG. 14A includes, over a substrate 5300, a pixel portion 5301 including a plurality of pixels that are each provided with a display element; a scan line driver circuit 5302 that selects a pixel; and a signal line driver circuit 5303 that controls a video signal input to the selected pixel.

The pixel portion 5301 is connected to the signal line driver circuit 5303 by a plurality of signal lines S1 to Sm (not illustrated) that extend in a column direction from the signal line driver circuit 5303, and to the scan line driver circuit 5302 by a plurality of scan lines G1 to Gn (not illustrated) that extend in a row direction from the scan line driver circuit 5302. The pixel portion 5301 includes a plurality of pixels (not illustrated) arranged in matrix so as to correspond to the signal lines S1 to Sm and the scan lines G1 to Gn. Each pixel is connected to a signal line Sj (one of the signal lines S1 to Sm) and a scan line Gi (one of the scan lines G1 to Gn).

In addition, the thin film transistor described in any of Embodiments 1 to 4 is an n-channel TFT, and a signal line driver circuit including the n-channel TFT is described with reference to FIG. 15.

The signal line driver circuit illustrated in FIG. 15 includes a driver IC 5601, switch groups 5602_1 to 5602_M, a first wiring 5611, a second wiring 5612, a third wiring 5613, and wirings 5621_1 to 5621_M. Each of the switch groups 5602_1 to 5602_M includes a first thin film transistor 5603 a, a second thin film transistor 5603 b, and a third thin film transistor 5603 c.

The driver IC 5601 is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M. Each of the switch groups 5602_1 to 5602_M is connected to the first wiring 5611, the second wiring 5612, and the third wiring 5613, and the wirings 5621_1 to 5621_M are connected to the switch groups 5602_1 to 5602_M, respectively. Each of the wirings 5621_1 to 5621_M is connected to three signal lines (a signal line Sm−2, a signal line Sm−1, and a signal line Sm (m=3M)) via the first thin film transistor 5603 a, the second thin film transistor 5603 b, and the third thin film transistor 5603 c. For example, the wiring 5621_J of the J-th column (one of the wirings 5621_1 to 5621_M) is connected to a signal line Sj−2, a signal line Sj−1, and a signal line Sj (j=3J) via the first thin film transistor 5603 a, the second thin film transistor 5603 b, and the third thin film transistor 5603 c which are included in the switch group 5602_J.

A signal is input to each of the first wiring 5611, the second wiring 5612, and the third wiring 5613.

Note that the driver IC 5601 is preferably formed using a single crystal semiconductor. The switch groups 5602_1 to 5602_M are preferably formed over the same substrate as the pixel portion. Therefore, the driver IC 5601 and the switch groups 5602_1 to 5602_M are preferably connected through an FPC or the like. Alternatively, the driver IC 5601 may be formed by providing a single crystal semiconductor layer over the same substrate as the pixel portion by a method such as bonding.

Next, operation of the signal line driver circuit illustrated in FIG. 15 is described with reference to a timing chart in FIG. 16. The timing chart in FIG. 16 illustrates a case where the scan line Gi of the i-th row is selected. A selection period of the scan line Gi of the i-th row is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. In addition, the signal line driver circuit in FIG. 15 operates similarly to that in FIG. 16 even when a scan line of another row is selected.

Note that the timing chart in FIG. 16 shows a case where the wiring 5621_J of the J-th column is connected to the signal line Sj−2, the signal line Sj−1, and the signal line Sj via the first thin film transistor 5603 a, the second thin film transistor 5603 b, and the third thin film transistor 5603 c.

The timing chart in FIG. 16 shows timing at which the scan line Gi of the i-th row is selected, timing 5703 a of on/off of the first thin film transistor 5603 a, timing 5703 b of on/off of the second thin film transistor 5603 b, timing 5703 c of on/off of the third thin film transistor 5603 c, and a signal 5721_J input to the wiring 5621_J of the J-th column.

In the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, different video signals are input to the wirings 5621_1 to 5621_M. For example, a video signal input to the wiring 5621_J in the first sub-selection period T1 is input to the signal line Sj−2, a video signal input to the wiring 5621_J in the second sub-selection period T2 is input to the signal line Sj−1, and a video signal input to the wiring 5621_J in the third sub-selection period T3 is input to the signal line Sj. In addition, the video signals input to the wiring 5621_J in the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 are denoted by Data_j−2, Data_j−1, and Data_j.

As illustrated in FIG. 16, in the first sub-selection period T1, the first thin film transistor 5603 a is turned on, and the second thin film transistor 5603 b and the third thin film transistor 5603 c are turned off. At this time, Data_j−2 input to the wiring 5621_J is input to the signal line Sj−2 via the first thin film transistor 5603 a. In the second sub-selection period T2, the second thin film transistor 5603 b is turned on, and the first thin film transistor 5603 a and the third thin film transistor 5603 c are turned off. At this time, Data_j−1 input to the wiring 5621_J is input to the signal line Sj−1 via the second thin film transistor 5603 b. In the third sub-selection period T3, the third thin film transistor 5603 c is turned on, and the first thin film transistor 5603 a and the second thin film transistor 5603 b are turned off. At this time, Data_j input to the wiring 5621_J is input to the signal line Sj via the third thin film transistor 5603 c.

As described above, in the signal line driver circuit in FIG. 15, by dividing one gate selection period into three, video signals can be input to three signal lines from one wiring 5621 in one gate selection period. Therefore, in the signal line driver circuit in FIG. 15, the number of connections between the substrate provided with the driver IC 5601 and the substrate provided with the pixel portion can be approximately ⅓ of the number of signal lines. The number of connections is reduced to approximately ⅓ of the number of the signal lines, so that reliability, yield, etc., of the signal line driver circuit in FIG. 15 can be improved.

Note that there are no particular limitations on the arrangement, the number, a driving method, and the like of the thin film transistors, as long as one gate selection period is divided into a plurality of sub-selection periods and video signals are input to a plurality of signal lines from one wiring in the respective sub-selection periods as illustrated in FIG. 15.

For example, when video signals are input to three or more signal lines from one wiring in each of three or more sub-selection periods, it is only necessary to add a thin film transistor and a wiring for controlling the thin film transistor. Note that when one gate selection period is divided into four or more sub-selection periods, one sub-selection period becomes short. Therefore, one gate selection period is preferably divided into two or three sub-selection periods.

As another example, one gate selection period may be divided into a precharge period Tp, the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 as illustrated in a timing chart in FIG. 17. The timing chart in FIG. 17 illustrates timing at which the scan line Gi of the i-th row is selected, timing 5803 a of on/off of the first thin film transistor 5603 a, timing 5803 b of on/off of the second thin film transistor 5603 b, timing 5803 c of on/off of the third thin film transistor 5603 c, and a signal 5821_J input to the wiring 5621_J of the J-th column. As illustrated in FIG. 17, the first thin film transistor 5603 a, the second thin film transistor 5603 b, and the third thin film transistor 5603 c are turned on in the precharge period Tp. At this time, precharge voltage Vp input to the wiring 5621_J is input to each of the signal line Sj−2, the signal line Sj−1, and the signal line Sj via the first thin film transistor 5603 a, the second thin film transistor 5603 b, and the third thin film transistor 5603 c. In the first sub-selection period T1, the first thin film transistor 5603 a is turned on, and the second thin film transistor 5603 b and the third thin film transistor 5603 c are turned off. At this time, Data_j−2 input to the wiring 5621_J is input to the signal line Sj−2 via the first thin film transistor 5603 a. In the second sub-selection period T2, the second thin film transistor 5603 b is turned on, and the first thin film transistor 5603 a and the third thin film transistor 5603 c are turned off. At this time, Data_j−1 input to the wiring 5621_J is input to the signal line Sj−1 via the second thin film transistor 5603 b. In the third sub-selection period T3, the third thin film transistor 5603 c is turned on, and the first thin film transistor 5603 a and the second thin film transistor 5603 b are turned off. At this time, Data_j input to the wiring 5621_J is input to the signal line Sj via the third thin film transistor 5603 c.

As described above, in the signal line driver circuit in FIG. 15 to which the timing chart in FIG. 17 is applied, the video signal can be written to the pixel at high speed because the signal line can be precharged by providing a precharge selection period before a sub-selection period. Note that portions in FIG. 17 which are similar to those of FIG. 16 are denoted by common reference numerals and detailed description of the same portions and portions which have similar functions is omitted.

Further, a structure of a scan line driver circuit is described. The scan line driver circuit includes a shift register and a buffer. Additionally, the scan line driver circuit may include a level shifter in some cases. In the scan line driver circuit, when the clock signal (CLK) and the start pulse signal (SP) are input to the shift register, a selection signal is produced. The selection signal produced is buffered and amplified by the buffer, and the resulting signal is supplied to a corresponding scan line. Gate electrodes of transistors in pixels of one line are connected to the scan line. Further, since the transistors in the pixels of one line have to be turned on at the same time, a buffer which can feed a large amount of current is used.

One mode of a shift register which is used for part of a scan line driver circuit is described with reference to FIG. 18 and FIG. 19.

FIG. 18 illustrates a circuit configuration of the shift register. The shift register illustrated in FIG. 18 includes a plurality of flip-flops, flip-flops 5701_1 to 5701 _(—) n. The shift register is operated with input of a first clock signal, a second clock signal, a start pulse signal, and a reset signal.

The connection relation of the shift register illustrated in FIG. 18 is described. The flip-flop 5701_1 of a first stage is connected to a first wiring 5711, a second wiring 5712, a fourth wiring 5714, a fifth wiring 5715, a seventh wiring 5717_1, and a seventh wiring 5717_2. The flip-flop 5717_2 of a second stage is connected to a third wiring 5713, the fourth wiring 5714, the fifth wiring 5715, the seventh wiring 5717_1, the seventh wiring 5717_2, and a seventh wiring 5717_3.

In a similar manner, the flip-flop 5701 _(—) i (any one of the flip-flops 5701_1 to 5701 _(—) n) of an i-th stage is connected to one of the second wiring 5712 and the third wiring 5713, the fourth wiring 5714, the fifth wiring 5715, a seventh wiring 5717 _(—) i−1, a seventh wiring 5717 _(—) i, and a seventh wiring 5717 _(—) i+1. Here, when the “i” is an odd number, the flip-flop 5701 _(—) i of the i-th stage is connected to the second wiring 5712; when the “i” is an even number, the flip-flop 5701 _(—) i of the i-th stage is connected to the third wiring 5713.

The flip-flop 5701 _(—) n of an n-th stage is connected to one of the second wiring 5712 and the third wiring 5713, the fourth wiring 5714, the fifth wiring 5715, a seventh wiring 5717 _(—) n−1, the seventh wiring 5717 _(—) n, and a sixth wiring 5716.

Note that the first wiring 5711, the second wiring 5712, the third wiring 5713, and the sixth wiring 5716 may be referred to as a first signal line, a second signal line, a third signal line, and a fourth signal line, respectively. The fourth wiring 5714 and the fifth wiring 5715 may be referred to as a first power supply line and a second power supply line, respectively.

Next, FIG. 19 illustrates details of the flip-flop illustrated in FIG. 18. A flip-flop illustrated in FIG. 19 includes a first thin film transistor 5571, a second thin film transistor 5572, a third thin film transistor 5573, a fourth thin film transistor 5574, a fifth thin film transistor 5575, a sixth thin film transistor 5576, a seventh thin film transistor 5577, and an eighth thin film transistor 5578. Each of the first thin film transistor 5571, the second thin film transistor 5572, the third thin film transistor 5573, the fourth thin film transistor 5574, the fifth thin film transistor 5575, the sixth thin film transistor 5576, the seventh thin film transistor 5577, and the eighth thin film transistor 5578 is an n-channel transistor and is turned on when the gate-source voltage (V_(gs)) exceeds the threshold voltage (V_(th)).

In addition, the flip-flop illustrated in FIG. 19 includes a first wiring 5501, a second wiring 5502, a third wiring 5503, a fourth wiring 5504, a fifth wiring 5505, and a sixth wiring 5506.

Note that all thin film transistors here are enhancement-mode n-channel transistors; however, the present invention is not limited thereto. For example, the driver circuit can be operated using depression-mode n-channel transistors.

Next, connections of the flip-flop illustrated in FIG. 18 are described below.

A first electrode (one of a source electrode and a drain electrode) of the first thin film transistor 5571 is connected to the fourth wiring 5504. A second electrode (the other of the source electrode and the drain electrode) of the first thin film transistor 5571 is connected to the third wiring 5503.

A first electrode of the second thin film transistor 5572 is connected to the sixth wiring 5506. A second electrode of the second thin film transistor 5572 is connected to the third wiring 5503.

A first electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505. A second electrode of the third thin film transistor 5573 is connected to a gate electrode of the second thin film transistor 5572. A gate electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505.

A first electrode of the fourth thin film transistor 5574 is connected to the sixth wiring 5506. A second electrode of the fourth thin film transistor 5574 is connected to the gate electrode of the second thin film transistor 5572. A gate electrode of the fourth thin film transistor 5574 is connected to a gate electrode of the first thin film transistor 5571.

A first electrode of the fifth thin film transistor 5575 is connected to the fifth wiring 5505. A second electrode of the fifth thin film transistor 5575 is connected to the gate electrode of the first thin film transistor 5571. A gate electrode of the fifth thin film transistor 5575 is connected to the first wiring 5501.

A first electrode of the sixth thin film transistor 5576 is connected to the sixth wiring 5506. A second electrode of the sixth thin film transistor 5576 is connected to the gate electrode of the first thin film transistor 5571. A gate electrode of the sixth thin film transistor 5576 is connected to the gate electrode of the second thin film transistor 5572.

A first electrode of the seventh thin film transistor 5577 is connected to the sixth wiring 5506. A second electrode of the seventh thin film transistor 5577 is connected to the gate electrode of the first thin film transistor 5571. A gate electrode of the seventh thin film transistor 5577 is connected to the second wiring 5502. A first electrode of the eighth thin film transistor 5578 is connected to the sixth wiring 5506. A second electrode of the eighth thin film transistor 5578 is connected to the gate electrode of the second thin film transistor 5572. A gate electrode of the eighth thin film transistor 5578 is connected to the first wiring 5501.

Note that the points at which the gate electrode of the first thin film transistor 5571, the gate electrode of the fourth thin film transistor 5574, the second electrode of the fifth thin film transistor 5575, the second electrode of the sixth thin film transistor 5576, and the second electrode of the seventh thin film transistor 5577 are connected are each referred to as a node 5543. The points at which the gate electrode of the second thin film transistor 5572, the second electrode of the third thin film transistor 5573, the second electrode of the fourth thin film transistor 5574, the gate electrode of the sixth thin film transistor 5576, and the second electrode of the eighth thin film transistor 5578 are connected are each referred to as a node 5544.

Note that the first wiring 5501, the second wiring 5502, the third wiring 5503, and the fourth wiring 5504 may be referred to as a first signal line, a second signal line, a third signal line, and a fourth signal line, respectively. The fifth wiring 5505 and the sixth wiring 5506 may be referred to as a first power supply line and a second power supply line, respectively.

In the flip-flop 5701 _(—) i of the i-th stage, the first wiring 5501 in FIG. 19 is connected to the seventh wiring 5717 _(—) i−1 in FIG. 18. The second wiring 5502 in FIG. 19 is connected to the seventh wiring 5717 _(—) i+1 in FIG. 18. The third wiring 5503 in FIG. 19 is connected to the seventh wiring 5717 _(—) i. The sixth wiring 5506 in FIG. 19 is connected to the fifth wiring 5715.

If the “i” is an odd number, the fourth wiring 5504 in FIG. 19 is connected to the second wiring 5712 in FIG. 18; if the “i” is an even number, the fourth wiring 5504 in FIG. 19 is connected to the third wiring 5713 in FIG. 18. In addition, the fifth wiring 5505 in FIG. 19 is connected to the fourth wiring 5714 in FIG. 18.

Note that in the flip-flop 5701_1 of the first stage, the first wiring 5501 in FIG. 19 is connected to the first wiring 5711 in FIG. 18. In addition, in the flip-flop 5701 _(—) n of the n-th stage, the second wiring 5502 in FIG. 19 is connected to the sixth wiring 5716 in FIG. 18.

In addition, the signal line driver circuit and the scan line driver circuit can be formed using only the n-channel TFTs described in any of Embodiments 1 to 4. The n-channel TFT described in any of Embodiments 1 to 4 has high mobility, and thus a driving frequency of a driver circuit can be increased. Further, parasitic capacitance is reduced by the source or drain region which is an In—Ga—Zn—O-based non-single-crystal film; thus, the n-channel TFT described in any of Embodiments 1 to 4 has high frequency characteristics (referred to as f characteristics). For example, a scan line driver circuit using the n-channel TFT described in any of Embodiments 1 to 4 can operate at high speed, and thus a frame frequency can be increased and insertion of black images can be realized.

In addition, when the channel width of the transistor in the scan line driver circuit is increased or a plurality of scan line driver circuits are provided, for example, higher frame frequency can be realized. When a plurality of scan line driver circuits are provided, a scan line driver circuit for driving scan lines of even-numbered rows is provided on one side and a scan line driver circuit for driving scan lines of odd-numbered rows is provided on the opposite side; thus, increase in frame frequency can be realized. Furthermore, the use of the plurality of scan line driver circuits for output of signals to the same scan line is advantageous in increasing the size of a display device.

Further, when an active matrix light-emitting display device which is an example of a semiconductor device is manufactured, a plurality of thin film transistors are arranged in at least one pixel, and thus a plurality of scan line driver circuits are preferably arranged. FIG. 14B is a block diagram illustrating an example of an active matrix light-emitting display device.

The light-emitting display device illustrated in FIG. 14B includes, over a substrate 5400, a pixel portion 5401 having a plurality of pixels each provided with a display element, a first scan line driver circuit 5402 and a second scan line driver circuit 5404 that select a pixel, and a signal line driver circuit 5403 that controls input of a video signal to the selected pixel.

When the video signal input to a pixel of the light-emitting display device illustrated in FIG. 14B is a digital signal, a pixel is in a light-emitting state or in a non-light-emitting state by switching of on/off of a transistor. Thus, grayscale can be displayed using an area ratio grayscale method or a time ratio grayscale method. An area ratio grayscale method refers to a driving method by which one pixel is divided into a plurality of subpixels and the respective subpixels are driven independently based on video signals so that grayscale is displayed. A time ratio grayscale method refers to a driving method by which a period during which a pixel is in a light-emitting state is controlled so that grayscale is displayed.

Since the response speed of light-emitting elements is higher than that of liquid crystal elements or the like, the light-emitting elements are more suitable for a time ratio grayscale method than liquid crystal display elements. Specifically, in the case of displaying with a time gray scale method, one frame period is divided into a plurality of subframe periods. Then, in accordance with video signals, the light-emitting element in the pixel is set in a light-emitting state or in a non-light-emitting state during each subframe period. By dividing one frame into a plurality of subframes, the total length of time, in which pixels actually emit light in one frame period, can be controlled with video signals so that gray scales are displayed.

In the example of the light-emitting display device illustrated in FIG. 14B, in a case where two switching TFTs are arranged in one pixel, the first scan line driver circuit 5402 generates a signal which is input to a first scan line serving as a gate wiring of one of the switching TFTs, and the second scan line driver circuit 5404 generates a signal which is input to a second scan line serving as a gate wiring of the other of the switching TFTs; however, one scan line driver circuit may generate both the signal which is input to the first scan line and the signal which is input to the second scan line. In addition, for example, there is a possibility that a plurality of scan lines used for controlling the operation of the switching elements be provided in each pixel depending on the number of switching TFTs included in one pixel. In that case, one scan line driver circuit may generate all signals that are input to the plurality of scan lines, or a plurality of scan line driver circuits may generate signals that are input to the plurality of scan lines.

In addition, also in the light-emitting display device, part of the driver circuit that can include n-channel TFTs among driver circuits can be formed over the same substrate as the thin film transistors of the pixel portion. Alternatively, the signal line driver circuit and the scan line driver circuit can be formed using only the n-channel TFTs described in any of Embodiments 1 to 4.

Moreover, the above-described driver circuit can be used for electronic paper that drives electronic ink using an element electrically connected to a switching element, without being limited to applications to a liquid crystal display device or a light-emitting display device. The electronic paper is also referred to as an electrophoretic display device (electrophoretic display) and has advantages in that it has the same level of readability as plain paper, it has lower power consumption than other display devices, and it can be made thin and lightweight.

Electrophoretic displays can have various modes. Electrophoretic displays contain a plurality of microcapsules dispersed in a solvent or a solute, each microcapsule containing first particles which are positively charged and second particles which are negatively charged. By applying an electric field to the microcapsules, the particles in the microcapsules are moved in opposite directions to each other and only the color of the particles concentrated on one side is exhibited. Note that the first particles and the second particles each contain pigment and do not move without an electric field. Moreover, the colors of the first particles and the second particles are different from each other (the colors include colorless or achroma).

In this way, an electrophoretic display is a display that utilizes a so-called dielectrophoretic effect by which a substance that has a high dielectric constant moves to a high-electric field region.

A solution in which the aforementioned microcapsules are dispersed throughout a solvent is referred to as electronic ink. This electronic ink can be printed on a surface of glass, plastic, cloth, paper, or the like. Furthermore, by use of a color filter or particles that have a pigment, color display is possible, as well.

In addition, if a plurality of the aforementioned microcapsules are arranged as appropriate over an active matrix substrate so as to be interposed between two electrodes, an active matrix display device can be completed, and display can be performed by application of an electric field to the microcapsules. For example, the active matrix substrate obtained with the thin film transistor described in any of Embodiments 1 to 4 can be used.

Note that the first particles and the second particles in the microcapsules may each be formed of a single material selected from a conductive material, an insulating material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, or a magnetophoretic material or formed of a composite material of any of these.

Through the above steps, a highly reliable display device as a semiconductor device can be manufactured.

Note that the structure described in this embodiment can be combined with any of the structures described in another embodiment as appropriate.

Embodiment 6

The thin film transistor described in any of Embodiments 1 to 4 is manufactured, and a semiconductor device having a display function (also referred to as a display device) can be manufactured using the thin film transistor in a pixel portion and further in a driver circuit. Further, part or whole of a driver circuit can be formed over the same substrate as a pixel portion, using the thin film transistor described in any of Embodiments 1 to 4, whereby a system-on-panel can be obtained.

The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light-emitting element (also referred to as a light-emitting display element) can be used. Light-emitting elements include, in its category, an element whose luminance is controlled by current or voltage, and specifically include an inorganic electroluminescent (EL) element, an organic EL element, and the like. Further, a display medium whose contrast is changed by an electric effect, such as an electronic ink, can be used.

In addition, the display device includes a panel in which the display element is sealed, and a module in which an IC including a controller or the like is mounted on the panel. An embodiment of the present invention relates to one embodiment of an element substrate before the display element is completed in a manufacturing process of the display device, and the element substrate is provided with means for supplying current to the display element in each of a plurality of pixels. Specifically, the element substrate may be in a state provided with only a pixel electrode of the display element, a state after a conductive film to be a pixel electrode is formed and before the conductive film is etched to form the pixel electrode, or any of other states.

Note that a display device in this specification means an image display device, a display device, or a light source (including a lighting device). Further, the display device includes any of the following modules in its category: a module to which a connector such as a flexible printed circuit (FPC), tape automated bonding (TAB) tape, or a tape carrier package (TCP) is attached; a module having TAB tape or a TCP which is provided with a printed wiring board at the end thereof; and a module having an integrated circuit (IC) which is directly mounted on a display element by a chip on glass (COG) method.

In this embodiment, the appearance and a cross section of a liquid crystal display panel, which is one embodiment of a semiconductor device, will be described with reference to FIGS. 22A-1, 22A-2, and 22B. FIGS. 22A-1 and 22A-2 are top views of a panel in which highly reliable thin film transistors 4010 and 4011 each including the In—Ga—Zn—O-based non-single-crystal film described in any of Embodiments 1 to 4 as an oxide semiconductor layer and a liquid crystal element 4013 formed over a first substrate 4001 are sealed between the first substrate 4001 and a second substrate 4006 with a sealant 4005. FIG. 22B is a cross-sectional view taken along line M-N of FIGS. 22A-1 and 22A-2.

The sealant 4005 is provided so as to surround a pixel portion 4002 and a scan line driver circuit 4004 which are provided over the first substrate 4001. The second substrate 4006 is provided over the pixel portion 4002 and the scan line driver circuit 4004. Therefore, the pixel portion 4002 and the scan line driver circuit 4004 are sealed together with a liquid crystal layer 4008, by the first substrate 4001, the sealant 4005, and the second substrate 4006. A signal line driver circuit 4003 that is formed using a single crystal semiconductor film or a polycrystalline semiconductor film over a substrate separately prepared is mounted in a region that is different from the region surrounded by the sealant 4005 over the first substrate 4001.

Note that the connection method of a driver circuit which is separately formed is not particularly limited, and a COG method, a wire bonding method, a TAB method, or the like can be used. FIGS. 22A-1 illustrates an example of mounting the signal line driver circuit 4003 by a COG method, and FIGS. 22A-2 illustrates an example of mounting the signal line driver circuit 4003 by a TAB method.

The pixel portion 4002 and the scan line driver circuit 4004 provided over the first substrate 4001 include a plurality of thin film transistors. FIG. 22B illustrates the thin film transistor 4010 included in the pixel portion 4002 and the thin film transistor 4011 included in the scan line driver circuit 4004. Over the thin film transistors 4010 and 4011, insulating layers 4020 and 4021 are provided.

The highly reliable thin film transistor including an In—Ga—Zn—O-based non-single-crystal film as an oxide semiconductor layer, which is described in any of Embodiments 1 to 4, can be applied to each of the thin film transistors 4010 and 4011. In this embodiment, the thin film transistors 4010 and 4011 are n-channel thin film transistors.

A pixel electrode layer 4030 included in the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. A counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 4006. A portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap one another corresponds to the liquid crystal element 4013. Note that the pixel electrode layer 4030 and the counter electrode layer 4031 are provided with an insulating layer 4032 and an insulating layer 4033 respectively which each function as an alignment film, and the liquid crystal layer 4008 is sandwiched between the pixel electrode layer 4030 and the counter electrode layer 4031 with the insulating layers 4032 and 4033 interposed therebetween.

Note that the first substrate 4001 and the second substrate 4006 can be formed by using glass, metal (typically, stainless steel), ceramic, or plastic. As plastic, a fiberglass-reinforced plastics (FRP) plate, a polyvinyl fluoride (PVF) film, a polyester film, or an acrylic resin film can be used. In addition, a sheet with a structure in which an aluminum foil is sandwiched between PVF films or polyester films can be used.

Reference numeral 4035 denotes a columnar spacer obtained by selectively etching an insulating film and is provided to control the distance between the pixel electrode layer 4030 and the counter electrode layer 4031 (a cell gap). Further, a spherical spacer may also be used. The counter electrode layer 4031 is electrically connected to a common potential line provided over the same substrate as the thin film transistor 4010. With the use of the common connection portion, the counter electrode layer 4031 is electrically connected to the common potential line through conductive particles provided between the pair of substrates. Note that the conductive particles are contained in the sealant 4005.

Alternatively, liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. A blue phase is one of liquid crystal phases, which is generated just before a cholesteric phase changes into an isotropic phase while temperature of cholesteric liquid crystal is increased. Since the blue phase is generated within an only narrow range of temperature, liquid crystal composition containing a chiral agent at 5 wt % or more so as to improve the temperature range is used for the liquid crystal layer 4008. The liquid crystal composition which includes liquid crystal exhibiting a blue phase and a chiral agent have such characteristics that the response time is 10 μs to 100 μs, which is short, the alignment process is unnecessary because the liquid crystal composition has optical isotropy, and viewing angle dependency is small.

Although an example of a transmissive liquid crystal display device is described in this embodiment, a reflective liquid crystal display device and a transflective liquid crystal display device can also be employed.

While an example of the liquid crystal display device in which the polarizing plate is provided on the outer side of the substrate (on the viewer side) and the coloring layer and the electrode layer used for a display element are provided on the inner side of the substrate in that order is described in this embodiment, the polarizing plate may be provided on the inner side of the substrate. The stacked structure of the polarizing plate and the coloring layer is not limited to this embodiment and may be set as appropriate depending on materials of the polarizing plate and the coloring layer or conditions of manufacturing steps. Further, a light-blocking film serving as a black matrix may be provided.

In this embodiment, in order to reduce surface unevenness of the thin film transistor and to improve reliability of the thin film transistor, the thin film transistor obtained in any of Embodiments 1 to 4 is covered with the insulating layers (the insulating layer 4020 and the insulating layer 4021) functioning as a protective film or a planarizing insulating film. Note that the protective film is provided to prevent entry of contaminant impurities such as an organic substance, a metal, or moisture floating in air and is preferably a dense film. The protective film may be formed with a single layer or a stacked layer of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, aluminum oxynitride film, and/or an aluminum nitride oxide film by a sputtering method. Although an example in which the protective film is formed by a sputtering method is described in this embodiment, the present invention is not limited to this example, and the protective film may be formed by a variety of methods.

In this embodiment, the insulating layer 4020 having a stacked-layer structure is formed as a protective film. Here, as a first layer of the insulating layer 4020, a silicon oxide film is formed by a sputtering method. The use of a silicon oxide film as a protective film has an effect of preventing hillock of an aluminum film used as the source and drain electrode layers.

As a second layer of the protective film, an insulating layer is formed. In this embodiment, as the second layer of the insulating layer 4020, a silicon nitride film is formed by a sputtering method. The use of the silicon nitride film as the protective film can prevent mobile ions of sodium or the like from entering a semiconductor region so that variation in electrical characteristics of the TFT can be suppressed.

After the protective film is formed, the oxide semiconductor layer may be subjected to annealing (300° C. to 400° C.).

The insulating layer 4021 is formed as the planarizing insulating film. As the insulating layer 4021, an organic material having heat resistance such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy can be used. Other than such organic materials, it is also possible to use a low-dielectric constant material (a low-k material), a siloxane-based resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), or the like. Note that the insulating layer 4021 may be formed by stacking a plurality of insulating films formed of these materials.

Note that a siloxane-based resin is a resin formed from a siloxane material as a starting material and having the bond of Si—O—Si. The siloxane-based resin may include an organic group (such as an alkyl group and an aryl group) or a fluoro group as a substituent. The organic group may include a fluoro group.

A formation method of the insulating layer 4021 is not particularly limited, and the following method can be employed depending on the material: a sputtering method, an SOG method, a spin coating method, a dipping method, a spray coating method, a droplet discharge method (e.g., an ink-jet method, screen printing, offset printing, or the like), a doctor knife, a roll coater, a curtain coater, a knife coater, or the like. In the case of forming the insulating layer 4021 using a material solution, annealing (300° C. to 400° C.) of the oxide semiconductor layer may be performed at the same time as a baking step. The baking step of the insulating layer 4021 also serves as annealing of the oxide semiconductor layer, whereby a semiconductor device can be manufactured efficiently.

The pixel electrode layer 4030 and the counter electrode layer 4031 can be formed using a light-transmitting conductive material such as indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide to which silicon oxide is added, or the like.

A conductive composition including a conductive high molecule (also referred to as a conductive polymer) can be used for the pixel electrode layer 4030 and the counter electrode layer 4031. The pixel electrode formed using the conductive composition preferably has a sheet resistance of less than or equal to 10000 ohm/square and a transmittance of greater than or equal to 70% at a wavelength of 550 nm. Further, the resistivity of the conductive high molecule included in the conductive composition is preferably less than or equal to 0.1 Ω·cm.

As the conductive high molecule, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, a copolymer of two or more kinds of them, and the like can be given.

Further, a variety of signals and potentials are supplied to the signal line driver circuit 4003 which is formed separately, the scan line driver circuit 4004, or the pixel portion 4002 from an FPC 4018.

In this embodiment, a connection terminal electrode 4015 is formed from the same conductive film as that of the pixel electrode layer 4030 included in the liquid crystal element 4013, and a terminal electrode 4016 is formed from the same conductive film as that of the source and drain electrode layers of the thin film transistors 4010 and 4011.

The connection terminal electrode 4015 is electrically connected to a terminal included in the FPC 4018 through an anisotropic conductive film 4019.

FIGS. 22A-1, 22A-2, and 22B illustrate an example in which the signal line driver circuit 4003 is formed separately and mounted on the first substrate 4001; however, this embodiment is not limited to this structure. The scan line driver circuit may be separately formed and then mounted, or only part of the signal line driver circuit or part of the scan line driver circuit may be separately formed and then mounted.

FIG. 23 illustrates an example in which a liquid crystal display module is formed as a semiconductor device by using a TFT substrate 2600 manufactured by application of the TFT described in any of Embodiments 1 to 4.

FIG. 23 illustrates an example of a liquid crystal display module, in which the TFT substrate 2600 and a counter substrate 2601 are fixed to each other with a sealant 2602, and a pixel portion 2603 including a TFT or the like, a display element 2604 including a liquid crystal layer, and a coloring layer 2605 are provided between the substrates to form a display region. The coloring layer 2605 is necessary to perform color display. In the case of the RGB system, respective coloring layers corresponding to colors of red, green, and blue are provided for respective pixels. Polarizing plates 2606 and 2607 and a diffusion plate 2613 are provided outside the TFT substrate 2600 and the counter substrate 2601. A light source includes a cold cathode tube 2610 and a reflective plate 2611, and a circuit substrate 2612 is connected to a wiring circuit portion 2608 of the TFT substrate 2600 through a flexible wiring board 2609 and includes an external circuit such as a control circuit or a power source circuit. The polarizing plate and the liquid crystal layer may be stacked with a retardation plate interposed therebetween.

For the liquid crystal display module, a twisted nematic (TN) mode, an in-plane-switching (IPS) mode, a fringe field switching (FFS) mode, a multi-domain vertical alignment (MVA) mode, a patterned vertical alignment (PVA) mode, an axially symmetric aligned micro-cell (ASM) mode, an optical compensated birefringence (OCB) mode, a ferroelectric liquid crystal (FLC) mode, an antiferroelectric liquid crystal (AFLC) mode, or the like can be used.

Through this process, a highly reliable liquid crystal display panel as a semiconductor device can be manufactured.

Note that the structure described in this embodiment can be combined with any of the structures described in another embodiment as appropriate.

Embodiment 7

In this embodiment, an example of electronic paper will be described as a semiconductor device to which the thin film transistor described in any of Embodiments 1 to 4 is applied.

FIG. 13 illustrates active matrix electronic paper as an example of a semiconductor device. A thin film transistor 581 used for the semiconductor device can be manufactured by application of the thin film transistor described in any of Embodiments 1 to 4.

The electronic paper in FIG. 13 is an example of a display device using a twisting ball display system. The twisting ball display system refers to a method in which spherical particles each colored in black or white are arranged between a first electrode layer and a second electrode layer which are electrode layers used for a display element, and a potential difference is generated between the first electrode layer and the second electrode layer to control orientation of the spherical particles, so that display is performed.

The thin film transistor 581 which is sealed between a substrate 580 and a substrate 596 is a thin film transistor with a bottom gate structure, and a source or drain electrode layer thereof is in contact with a first electrode layer 587 through an opening formed in insulating layers 583, 584, and 585, whereby the thin film transistor 581 is electrically connected to the first electrode layer 587. Between the first electrode layer 587 and a second electrode layer 588, spherical particles 589 each having a black region 590 a, a white region 590 b, and a cavity 594 around the regions which is filled with liquid are provided. A space around the spherical particles 589 is filled with a filler 595 such as a resin (see FIG. 13). In this embodiment, the first electrode layer 587 corresponds to the pixel electrode and the second electrode layer 588 corresponds to the common electrode. The second electrode layer 588 is electrically connected to a common potential line provided over the same substrate as the thin film transistor 581. With the use of the common connection portion, the second electrode layer 588 is electrically connected to the common potential line through conductive particles provided between the pair of substrates.

Further, instead of the twisting ball, an electrophoretic element can also be used. A microcapsule having a diameter of about 10 μm to 200 μm in which transparent liquid, positively charged white microparticles, and negatively charged black microparticles are encapsulated, is used. In the microcapsule which is provided between the first electrode layer and the second electrode layer, when an electric field is applied by the first electrode layer and the second electrode layer, the white microparticles and the black microparticles move to opposite sides, so that white or black can be displayed. A display element using this principle is an electrophoretic display element and is called electronic paper in general. The electrophoretic display element has higher reflectance than a liquid crystal display element, and thus, an auxiliary light is unnecessary, power consumption is low, and a display portion can be recognized in a dim place. In addition, even when power is not supplied to the display portion, an image which has been displayed once can be maintained. Accordingly, a displayed image can be stored even if a semiconductor device having a display function (which may be referred to simply as a display device or a semiconductor device provided with a display device) is distanced from an electric wave source.

Through this process, highly reliable electronic paper as a semiconductor device can be manufactured.

Note that the structure described in this embodiment can be combined with any of the structures described in another embodiment as appropriate.

Embodiment 8

In this embodiment, an example of a light-emitting display device will be described as a semiconductor device to which the thin film transistor described in any of Embodiments 1 to 4 is applied. As a display element included in a display device, a light-emitting element utilizing electroluminescence is described here. Light-emitting elements utilizing electroluminescence are classified according to whether a light-emitting material is an organic compound or an inorganic compound. In general, the former is referred to as an organic EL element, and the latter is referred to as an inorganic EL element.

In an organic EL element, by application of voltage to a light-emitting element, electrons and holes are separately injected from a pair of electrodes into a layer containing a light-emitting organic compound, and current flows. The carriers (electrons and holes) are recombined, and thus, the light-emitting organic compound is excited. The light-emitting organic compound returns to a ground state from the excited state, thereby emitting light. Owing to such a mechanism, this light-emitting element is referred to as a current-excitation light-emitting element.

The inorganic EL elements are classified according to their element structures into a dispersion-type inorganic EL element and a thin-film inorganic EL element. A dispersion-type inorganic EL element has a light-emitting layer where particles of a light-emitting material are dispersed in a binder, and its light emission mechanism is donor-acceptor recombination type light emission that utilizes a donor level and an acceptor level. A thin-film inorganic EL element has a structure where a light-emitting layer is sandwiched between dielectric layers, which are further sandwiched between electrodes, and its light emission mechanism is localized type light emission that utilizes inner-shell electron transition of metal ions. Note that description is made here using an organic EL element as a light-emitting element.

FIG. 20 illustrates an example of a pixel structure to which digital time grayscale driving can be applied, as an example of a semiconductor device to which an embodiment of the present invention is applied.

A structure and operation of a pixel to which digital time grayscale driving can be applied are described. Here, one pixel includes two n-channel transistors each of which includes an oxide semiconductor layer (an In—Ga—Zn—O-based non-single-crystal film) in a channel formation region and each of which is described in any of Embodiments 1 to 4.

A pixel 6400 includes a switching transistor 6401, a driver transistor 6402, a light-emitting element 6404, and a capacitor 6403. A gate of the switching transistor 6401 is connected to a scan line 6406, a first electrode (one of a source electrode and a drain electrode) of the switching transistor 6401 is connected to a signal line 6405, and a second electrode (the other of the source electrode and the drain electrode) of the switching transistor 6401 is connected to a gate of the driver transistor 6402. The gate of the driver transistor 6402 is connected to a power supply line 6407 through the capacitor 6403, a first electrode of the driver transistor 6402 is connected to the power supply line 6407, and a second electrode of the driver transistor 6402 is connected to a first electrode (pixel electrode) of the light-emitting element 6404. A second electrode of the light-emitting element 6404 corresponds to a common electrode 6408. The common electrode 6408 is electrically connected to a common potential line provided over the same substrate, and the structure illustrated in FIG. 1A, FIG. 2A, or FIG. 3A may be obtained using the connection portion as a common connection portion.

The second electrode (the common electrode 6408) of the light-emitting element 6404 is set to a low power supply potential. Note that the low power supply potential is a potential satisfying the low power supply potential<a high power supply potential with reference to the high power supply potential that is set to the power supply line 6407. As the low power supply potential, GND, 0 V, or the like may be employed, for example. A potential difference between the high power supply potential and the low power supply potential is applied to the light-emitting element 6404 and current is supplied to the light-emitting element 6404, so that the light-emitting element 6404 emits light. Here, in order to make the light-emitting element 6404 emit light, each potential is set so that the potential difference between the high power supply potential and the low power supply potential is a forward threshold voltage or higher.

Note that gate capacitance of the driver transistor 6402 may be used as a substitute for the capacitor 6403, so that the capacitor 6403 can be omitted. The gate capacitance of the driver transistor 6402 may be formed between the channel region and the gate electrode.

In the case of a voltage-input voltage driving method, a video signal is input to the gate of the driver transistor 6402 so that the driver transistor 6402 is in either of two states of being sufficiently turned on and turned off. That is, the driver transistor 6402 operates in a linear region. Since the driver transistor 6402 operates in a linear region, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the driver transistor 6402. Note that a voltage higher than or equal to (voltage of the power supply line +Vth of the driver transistor 6402) is applied to the signal line 6405.

In the case of performing analog grayscale driving instead of digital time grayscale driving, the same pixel structure as that in FIG. 20 can be used by changing signal input.

In the case of performing analog grayscale driving, a voltage higher than or equal to (forward voltage of the light-emitting element 6404+Vth of the driver transistor 6402) is applied to the gate of the driver transistor 6402. The forward voltage of the light-emitting element 6404 indicates a voltage at which a desired luminance is obtained, and includes at least forward threshold voltage. The video signal by which the driver transistor 6402 operates in a saturation region is input, so that current can be supplied to the light-emitting element 6404. In order for the driver transistor 6402 to operate in a saturation region, the potential of the power supply line 6407 is set higher than the gate potential of the driver transistor 6402. When an analog video signal is used, it is possible to feed current to the light-emitting element 6404 in accordance with the video signal and perform analog grayscale driving.

Note that the pixel structure illustrated in FIG. 20 is not limited thereto. For example, a switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be added to the pixel illustrated in FIG. 20.

Next, structures of the light-emitting element will be described with reference to FIGS. 21A to 21C. A cross-sectional structure of a pixel will be described by taking an n-channel driving TFT as an example. Driving TFTs 7001, 7011, and 7021 used for semiconductor devices illustrated in FIGS. 21A to 21C can be formed in a manner similar to formation of the thin film transistor described in any of Embodiments 1 to 4 and are highly reliable thin film transistors each including an In—Ga—Zn—O-based non-single-crystal film as an oxide semiconductor layer.

In order to extract light emitted from the light-emitting element, at least one of the anode and the cathode is required to transmit light. A thin film transistor and a light-emitting element are formed over a substrate. A light-emitting element can have a top emission structure, in which light emission is extracted through the surface opposite to the substrate; a bottom emission structure, in which light emission is extracted through the surface on the substrate side; or a dual emission structure, in which light emission is extracted through the surface opposite to the substrate and the surface on the substrate side. A pixel structure according to an embodiment of the present invention can be applied to a light-emitting element having any of these emission structures.

A light-emitting element having a top emission structure will be described with reference to FIG. 21A.

FIG. 21A is a cross-sectional view of a pixel in the case where the driving TFT 7001 is an n-channel TFT and light is emitted from a light-emitting element 7002 to an anode 7005 side. In FIG. 21A, a cathode 7003 of the light-emitting element 7002 is electrically connected to the driving TFT 7001, and a light-emitting layer 7004 and the anode 7005 are stacked in this order over the cathode 7003. The cathode 7003 can be formed using a variety of conductive materials as long as they have a low work function and reflect light. For example, Ca, Al, MgAg, AlLi, or the like is preferably used. The light-emitting layer 7004 may be formed using a single layer or a plurality of layers stacked. When the light-emitting layer 7004 is formed using a plurality of layers, the light-emitting layer 7004 is formed by stacking an electron-injecting layer, an electron-transporting layer, a light-emitting layer, a hole-transporting layer, and a hole-injecting layer in this order over the cathode 7003. It is not necessary to form all of these layers. The anode 7005 is formed using a light-transmitting conductive film such as a film of indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, or indium tin oxide to which silicon oxide is added.

The light-emitting element 7002 corresponds to a region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005. In the case of the pixel illustrated in FIG. 21A, light is emitted from the light-emitting element 7002 to the anode 7005 side as indicated by an arrow.

Next, a light-emitting element having a bottom emission structure will be described with reference to FIG. 21B. FIG. 21B is a cross-sectional view of a pixel in the case where the driving TFT 7011 is an n-channel transistor and light is emitted from a light-emitting element 7012 to a cathode 7013 side. In FIG. 21B, the cathode 7013 of the light-emitting element 7012 is formed over a light-transmitting conductive film 7017 that is electrically connected to the driving TFT 7011, and a light-emitting layer 7014 and an anode 7015 are stacked in this order over the cathode 7013. A light-blocking film 7016 for reflecting or blocking light may be formed to cover the anode 7015 when the anode 7015 has a light-transmitting property. For the cathode 7013, a variety of materials can be used as in the case of FIG. 21A as long as they are conductive materials having a low work function. The cathode 7013 is formed to have a thickness that can transmit light (preferably, approximately 5 nm to 30 nm) For example, an aluminum film with a thickness of 20 nm can be used as the cathode 7013. In a manner similar to the case of FIG. 21A, the light-emitting layer 7014 may be formed using either a single layer or a plurality of layers stacked. The anode 7015 is not required to transmit light, but can be formed using a light-transmitting conductive material as in the case of FIG. 21A. As the light-blocking film 7016, a metal or the like that reflects light can be used for example; however, it is not limited to a metal film. For example, a resin or the like to which black pigments are added can also be used.

The light-emitting element 7012 corresponds to a region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015. In the case of the pixel illustrated in FIG. 21B, light is emitted from the light-emitting element 7012 to the cathode 7013 side as indicated by an arrow.

Next, a light-emitting element having a dual emission structure will be described with reference to FIG. 21C. In FIG. 21C, a cathode 7023 of a light-emitting element 7022 is formed over a light-transmitting conductive film 7027 which is electrically connected to the driving TFT 7021, and a light-emitting layer 7024 and an anode 7025 are stacked in this order over the cathode 7023. As in the case of FIG. 21A, the cathode 7023 can be formed using a variety of conductive materials as long as they have a low work function. The cathode 7023 is formed to have a thickness that can transmit light. For example, a film of Al having a thickness of 20 nm can be used as the cathode 7023. As in the case of FIG. 21A, the light-emitting layer 7024 may be formed using either a single layer or a plurality of layers stacked. The anode 7025 can be formed using a light-transmitting conductive material as in the case of FIG. 21A.

The light-emitting element 7022 corresponds to a region where the cathode 7023, the light-emitting layer 7024, and the anode 7025 overlap with one another. In the case of the pixel illustrated in FIG. 21C, light is emitted from the light-emitting element 7022 to both the anode 7025 side and the cathode 7023 side as indicated by arrows.

Note that, although an organic EL element is described here as a light-emitting element, an inorganic EL element can also be provided as a light-emitting element.

In this embodiment, the example is described in which a thin film transistor (a driving TFT) which controls the driving of a light-emitting element is electrically connected to the light-emitting element; however, a structure may be employed in which a TFT for current control is connected between the driving TFT and the light-emitting element.

A semiconductor device described in this embodiment is not limited to the structures illustrated in FIGS. 21A to 21C and can be modified in various ways based on the spirit of techniques according to the present invention.

Next, the appearance and a cross section of a light-emitting display panel (also referred to as a light-emitting panel), which is one embodiment of a semiconductor device to which the thin film transistor described in any of Embodiments 1 to 4 is applied, will be described with reference to FIGS. 24A and 24B. FIG. 24A is a top view of a panel in which a thin film transistor and a light-emitting element formed over a first substrate are sealed between the first substrate and a second substrate with a sealant. FIG. 24B is a cross-sectional view taken along line H-I of FIG. 24A.

A sealant 4505 is provided so as to surround a pixel portion 4502, signal line driver circuits 4503 a and 4503 b, and scan line driver circuits 4504 a and 4504 b which are provided over a first substrate 4501. In addition, a second substrate 4506 is provided over the pixel portion 4502, the signal line driver circuits 4503 a and 4503 b, and the scan line driver circuits 4504 a and 4504 b. Accordingly, the pixel portion 4502, the signal line driver circuits 4503 a and 4503 b, and the scan line driver circuits 4504 a and 4504 b are sealed together with a filler 4507, by the first substrate 4501, the sealant 4505, and the second substrate 4506. It is preferable that a panel be packaged (sealed) with a protective film (such as a laminate film or an ultraviolet curable resin film) or a cover material with high air-tightness and little degasification so that the panel is not exposed to the outside air as described above.

The pixel portion 4502, the signal line driver circuits 4503 a and 4503 b, and the scan line driver circuits 4504 a and 4504 b formed over the first substrate 4501 each include a plurality of thin film transistors, and a thin film transistor 4510 included in the pixel portion 4502 and a thin film transistor 4509 included in the signal line driver circuit 4503 a are illustrated as an example in FIG. 24B.

The highly reliable thin film transistor including an In—Ga—Zn—O-based non-single-crystal film as an oxide semiconductor layer, which is described in any of Embodiments 1 to 4, can be employed as the thin film transistors 4509 and 4510. In this embodiment, the thin film transistors 4509 and 4510 are n-channel thin film transistors.

Moreover, reference numeral 4511 denotes a light-emitting element. A first electrode layer 4517 which is a pixel electrode included in the light-emitting element 4511 is electrically connected to a source electrode layer or a drain electrode layer of the thin film transistor 4510. Note that a structure of the light-emitting element 4511 is a stacked-layer structure of the first electrode layer 4517, an electroluminescent layer 4512, and a second electrode layer 4513, but the present invention is not limited to that described in this embodiment. The structure of the light-emitting element 4511 can be changed as appropriate depending on the direction in which light is extracted from the light-emitting element 4511, or the like.

A partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. It is particularly preferable that the partition wall 4520 be formed using a photosensitive material and an opening be formed over the first electrode layer 4517 so that a sidewall of the opening is formed as an inclined surface with continuous curvature.

The electroluminescent layer 4512 may be formed with a single layer or a plurality of layers stacked.

A protective film may be formed over the second electrode layer 4513 and the partition wall 4520 in order to prevent entry of oxygen, hydrogen, moisture, carbon dioxide, or the like into the light-emitting element 4511. As the protective film, a silicon nitride film, a silicon nitride oxide film, a DLC film, or the like can be formed.

In addition, a variety of signals and potentials are supplied to the signal line driver circuits 4503 a and 4503 b, the scan line driver circuits 4504 a and 4504 b, or the pixel portion 4502 from FPCs 4518 a and 4518 b.

In this embodiment, a connection terminal electrode 4515 is formed from the same conductive film as that of the first electrode layer 4517 included in the light-emitting element 4511, and a terminal electrode 4516 is formed from the same conductive film as that of the source and drain electrode layers included in the thin film transistors 4509 and 4510.

The connection terminal electrode 4515 is electrically connected to a terminal included in the FPC 4518 a through an anisotropic conductive film 4519.

The second substrate 4506 located in the direction in which light is extracted from the light-emitting element 4511 needs to have a light-transmitting property. In that case, a light-transmitting material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used.

As the filler 4507, an ultraviolet curable resin or a thermosetting resin can be used, in addition to an inert gas such as nitrogen or argon. For example, PVC (polyvinyl chloride), acrylic, polyimide, an epoxy resin, a silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. In this embodiment, nitrogen is used for the filler 4507.

In addition, if needed, an optical film, such as a polarizing plate, a circularly polarizing plate (including an elliptically polarizing plate), a retardation plate (a quarter-wave plate or a half-wave plate), or a color filter, may be provided as appropriate on a light-emitting surface of the light-emitting element. Further, the polarizing plate or the circularly polarizing plate may be provided with an anti-reflection film. For example, anti-glare treatment by which reflected light can be diffused by projections and depressions on the surface so as to reduce the glare can be performed.

The signal line driver circuits 4503 a and 4503 b and the scan line driver circuits 4504 a and 4504 b may be provided as driver circuits formed using a single crystal semiconductor film or polycrystalline semiconductor film over a substrate separately prepared. In addition, only the signal line driver circuits or part thereof, or only the scan line driver circuits or part thereof may be separately formed and mounted. This embodiment is not limited to the structure illustrated in FIGS. 24A and 24B.

Through this process, a highly reliable light-emitting display device (display panel) as a semiconductor device can be manufactured.

Note that the structure described in this embodiment can be combined with any of the structures described in another embodiment as appropriate.

Embodiment 9

A semiconductor device to which the thin film transistor described in any of Embodiments 1 to 4 is applied can be used as electronic paper. Electronic paper can be used for electronic devices of a variety of fields as long as they can display data. For example, electronic paper can be applied to an electronic book (e-book) reader, a poster, an advertisement in a vehicle such as a train, displays of various cards such as a credit card, and the like. Examples of the electronic devices are illustrated in FIGS. 25A and 25B and FIG. 26.

FIG. 25A illustrates a poster 2631 formed using electronic paper. In the case where an advertising medium is printed paper, the advertisement is replaced by manpower; however, by using electronic paper, the advertising display can be changed in a short time. Further, an image can be stably displayed without being distorted. Note that the poster may be configured to transmit and receive data wirelessly.

FIG. 25B illustrates an advertisement 2632 in a vehicle such as a train. In the case where an advertising medium is printed paper, the advertisement is replaced by manpower; however, by using electronic paper, the advertising display can be changed in a short time without a lot of manpower. Further, an image can be stably displayed without being distorted. Note that the advertisement in a vehicle may be configured to transmit and receive data wirelessly.

FIG. 26 illustrates an example of an electronic book reader 2700. For example, the electronic book reader 2700 includes two housings, a housing 2701 and a housing 2703. The housing 2701 and the housing 2703 are combined with a hinge 2711 so that the electronic book reader 2700 can be opened and closed with the hinge 2711 as an axis. With such a structure, the electronic book reader 2700 can be operated like a paper book.

A display portion 2705 and a display portion 2707 are incorporated in the housing 2701 and the housing 2703, respectively. The display portion 2705 and the display portion 2707 may be configured to display one image or different images. In the case where the display portion 2705 and the display portion 2707 display different images, for example, a display portion on the right side (the display portion 2705 in FIG. 26) can display text and a display portion on the left side (the display portion 2707 in FIG. 26) can display graphics.

FIG. 26 illustrates an example in which the housing 2701 is provided with an operation portion and the like. For example, the housing 2701 is provided with a power switch 2721, an operation key 2723, a speaker 2725, and the like. With the operation key 2723, pages can be turned. Note that a keyboard, a pointing device, or the like may be provided on the surface of the housing, on which the display portion is provided. Further, an external connection terminal (an earphone terminal, a USB terminal, a terminal that can be connected to various cables such as an AC adapter and a USB cable, or the like), a recording medium insert portion, or the like may be provided on the back surface or the side surface of the housing. Further, the electronic book reader 2700 may have a function of an electronic dictionary.

The electronic book reader 2700 may be configured to transmit and receive data wirelessly. The structure can be employed in which desired book data or the like is purchased and downloaded from an electronic book server wirelessly.

Note that the structure described in this embodiment can be combined with any of the structures described in another embodiment as appropriate.

Embodiment 10

A semiconductor device using the thin film transistor described in any of Embodiments 1 to 4 can be applied to a variety of electronic devices (including an amusement machine). Examples of electronic devices include a television set (also referred to as a television or a television receiver), a monitor of a computer or the like, a camera such as a digital camera or a digital video camera, a digital photo frame, a mobile phone handset (also referred to as a mobile phone or a mobile phone device), a portable game console, a portable information terminal, an audio reproducing device, a large-sized game machine such as a pachinko machine, and the like.

FIG. 27A illustrates an example of a television set 9600. In the television set 9600, a display portion 9603 is incorporated in a housing 9601. The display portion 9603 can display an image. Further, the housing 9601 is supported by a stand 9605 here.

The television set 9600 can be operated with an operation switch of the housing 9601 or a separate remote controller 9610. Channels and volume can be controlled with an operation key 9609 of the remote controller 9610 so that an image displayed on the display portion 9603 can be controlled. Further, the remote controller 9610 may be provided with a display portion 9607 for displaying data output from the remote controller 9610.

Note that the television set 9600 is provided with a receiver, a modem, and the like. With the receiver, a general television broadcast can be received. Further, when the television set 9600 is connected to a communication network by wired or wireless connection via the modem, one-way (from a transmitter to a receiver) or two-way (between a transmitter and a receiver or between receivers) data communication can be performed.

FIG. 27B illustrates an example of a digital photo frame 9700. For example, in the digital photo frame 9700, a display portion 9703 is incorporated in a housing 9701. The display portion 9703 can display various images. For example, the display portion 9703 can display data of an image taken with a digital camera or the like and function as a normal photo frame.

Note that the digital photo frame 9700 is provided with an operation portion, an external connection terminal (a USB terminal, a terminal that can be connected to various cables such as a USB cable, or the like), a recording medium insertion portion, and the like. Although these components may be provided on the surface on which the display portion is provided, it is preferable to provide them on the side surface or the back surface for the design of the digital photo frame 9700. For example, a memory storing data of an image taken with a digital camera is inserted in the recording medium insertion portion of the digital photo frame, whereby the image data can be transferred and then displayed on the display portion 9703.

The digital photo frame 9700 may be configured to transmit and receive data wirelessly. The structure may be employed in which desired image data is transferred wirelessly to be displayed.

FIG. 28A is a portable game machine and includes two housings, a housing 9881 and a housing 9891, which are connected with a joint portion 9893 so that the portable game machine can be opened or folded. A display portion 9882 is incorporated in the housing 9881, and a display portion 9883 is incorporated in the housing 9891. In addition, the portable game machine illustrated in FIG. 28A is provided with a speaker portion 9884, a recording medium insert portion 9886, an LED lamp 9890, input means (operation keys 9885, a connection terminal 9887, a sensor 9888 (having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation number, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electric power, radial ray, flow rate, humidity, gradient, vibration, odor, or infrared ray), and a microphone 9889), and the like. Needless to say, the structure of the portable game machine is not limited to that described above. The portable game machine may have a structure in which additional accessory equipment is provided as appropriate as long as at least a semiconductor device according to an embodiment of the present invention is provided. The portable game machine illustrated in FIG. 28A has a function of reading a program or data stored in a recording medium to display it on the display portion, and a function of sharing information with another portable game machine by wireless communication. Note that a function of the portable game machine illustrated in FIG. 28A is not limited to those described above, and the portable game machine can have a variety of functions.

FIG. 28B illustrates an example of a slot machine 9900 which is a large-sized amusement machine. In the slot machine 9900, a display portion 9903 is incorporated in a housing 9901. In addition, the slot machine 9900 is provided with operation means such as a start lever and a stop switch, a coin slot, a speaker, or the like. Needless to say, the structure of the slot machine 9900 is not limited to the above-described structure. The slot machine may have a structure in which additional accessory equipment is provided as appropriate as long as at least a semiconductor device according to an embodiment of the present invention is provided.

FIG. 29A illustrates an example of a mobile phone handset 1000. The mobile phone handset 1000 is provided with a display portion 1002 incorporated in a housing 1001, operation buttons 1003, an external connection port 1004, a speaker 1005, a microphone 1006, and the like.

When the display portion 1002 of the mobile phone handset 1000 illustrated in FIG. 29A is touched with a finger or the like, data can be input into the mobile phone handset 1000. Further, operation such as making calls and texting can be performed by touching the display portion 1002 with a finger or the like.

There are mainly three screen modes of the display portion 1002. The first mode is a display mode mainly for displaying an image. The second mode is an input mode mainly for inputting data such as text. The third mode is a display-and-input mode which is a combination of the two modes, that is, a combination of the display mode and the input mode.

For example, in the case of making a call or texting, a text input mode mainly for inputting text is selected for the display portion 1002 so that characters displayed on a screen can be inputted. In that case, it is preferable to display a keyboard or number buttons on almost all area of the screen of the display portion 1002.

When a detection device including a sensor for detecting inclination, such as a gyroscope or an acceleration sensor, is provided inside the mobile phone handset 1000, display on the screen of the display portion 1002 can be automatically changed by determining the orientation of the mobile phone handset 1000 (whether the mobile phone handset 1000 is placed horizontally or vertically for a landscape mode or a portrait mode).

The screen modes are changed by touching the display portion 1002 or using the operation buttons 1003 of the housing 1001. Alternatively, the screen modes may be changed depending on the kind of image displayed on the display portion 1002. For example, when a signal of an image displayed on the display portion is the one of moving image data, the screen mode is changed to the display mode. When the signal is the one of text data, the screen mode is changed to the input mode.

Further, in the input mode, when input by touching the display portion 1002 is not performed for a certain period while a signal detected by the optical sensor in the display portion 1002 is detected, the screen mode may be controlled so as to be changed from the input mode to the display mode.

The display portion 1002 may function as an image sensor. For example, an image of a palm print, a fingerprint, or the like is taken when the display portion 1002 is touched with a palm or a finger, whereby personal identification can be performed. Further, by providing a backlight or a sensing light source which emits a near-infrared light in the display portion, an image of a finger vein, a palm vein, or the like can be taken.

FIG. 29B illustrates another example of a cellular phone. The cellular phone in FIG. 29B has a display device 9410 in a housing 9411, which includes a display portion 9412 and operation buttons 9413, and a communication device 9400 in a housing 9401, which includes operation buttons 9402, an external input terminal 9403, a microphone 9404, a speaker 9405, and a light-emitting portion 9406 that emits light when a phone call is received. The display device 9410 which has a display function can be detached from or attached to the communication device 9400 which has a phone function by moving in two directions represented by allows. Thus, the display device 9410 and the communication device 9400 can be attached to each other along their short sides or long sides. In addition, when only the display function is needed, the display device 9410 can be detached from the communication device 9400 and used alone. Images or input information can be transmitted or received by wireless or wire communication between the communication device 9400 and the display device 9410, each of which has a rechargeable battery.

Note that the structure described in this embodiment can be combined with any of the structures described in another embodiment as appropriate.

Example 1

In this example, results in which dependence of electrical conductivity of an oxide semiconductor film on the proportion of the flow rate of an oxygen gas during film formation is measured are described.

In this example, In—Ga—Zn—O-based non-single-crystal films were formed by a sputtering method, and the electrical conductivity of the formed In—Ga—Zn—O-based non-single-crystal films was measured. Samples were formed under a condition where the proportion of the flow rate of an oxygen gas during film formation was changed from 0 volume % to 100 volume % among the samples, and each electrical conductivity of the In—Ga—Zn—O-based non-single-crystal films formed by varying the proportion of the flow rate of the oxygen gas among the samples was measured. Note that the electrical conductivity was measured using a semiconductor parameter analyzer HP4155C (made by Agilent Technologies Inc.).

The In—Ga—Zn—O-based non-single-crystal films were formed by sputtering, with use of a disk-shaped oxide semiconductor target of 8 inches in diameter, in which In₂O₃, Ga₂O₃, and ZnO are mixed in the ratio of In₂O₃:Ga₂O₃:ZnO=1:1:1 (In:Ga:Zn=1:1:0.5), as a target. Other film formation conditions are as follows: The distance between a substrate and the target was set to 170 mm, the pressure for a film-forming gas was set to 0.4 Pa, the direct-current (DC) power source was set to 0.5 kW, and the formation temperature was set to room temperature.

As a film-forming gas, an argon gas and an oxygen gas were used. Film formation was performed under the condition where the proportion of the flow rate of the oxygen gas in the argon gas and the oxygen gas was changed from 0 volume % to 100 volume % among the samples, and each electrical conductivity of the In—Ga—Zn—O-based non-single-crystal films was measured. Note that, in order to perform rearrangement at the atomic level on each of the In—Ga—Zn—O-based non-single-crystal films, heat treatment at 350° C. in a nitrogen atmosphere was performed for one hour after each of the In—Ga—Zn—O-based non-single-crystal films was formed.

Each electrical conductivity of the In—Ga—Zn—O-based non-single-crystal films formed by varying the proportion of the flow rate of the oxygen gas among the samples is shown in FIG. 12. In FIG. 12, the horizontal axis represents the proportion of the flow rate of the oxygen gas (volume %) in the flow rate of the argon gas and the flow rate of the oxygen gas, and the vertical axis represents the electrical conductivity (S/cm) of the In—Ga—Zn—O-based non-single-crystal films. Further, Table 1 is a table corresponding to FIG. 12, and shows the flow rate of the argon gas (sccm), the flow rate of the oxygen gas (sccm), the proportion of the flow rate of the oxygen gas (volume %), and the electrical conductivity of each of the In—Ga—Zn—O-based non-single-crystal films (S/cm).

TABLE 1 Proportion of flow rate of oxygen Conductivity Ar (sccm) O₂ (sccm) gas (volume %) (S/cm) 50 0 0 6.44 × 10⁰ 40 5 11.1 7.01 × 10⁻⁵ 40 10 20 5.24 × 10⁻⁵ 30 15 33.3 1.23 × 10⁻⁴ 30 20 40 3.98 × 10⁻⁵ 25 25 50 1.52 × 10⁻⁶ 20 30 60 2.92 × 10⁻⁷ 15 35 70 2.68 × 10⁻⁹ 10 40 80 2.57 × 10⁻¹⁰ 5 45 90 1.59 × 10⁻¹⁰ 0 50 100 4.19 × 10⁻¹¹

From the results in FIG. 12 and Table 1, when the proportion of the flow rate of the oxygen gas is 0 volume % to 11.1 volume %, the electrical conductivity is significantly decreased; when the proportion of the flow rate of the oxygen gas is 11.1 volume % to 40 volume %, the electrical conductivity is about 1.0×10⁻⁵ S/cm to 1.0×10⁻⁴ S/cm; and when the proportion of the flow rate of the oxygen gas is 40 volume % or higher, the electrical conductivity is gradually decreased. Note that, when the proportion of the flow rate of the oxygen gas is 60 volume % to 70 volume %, decrease in the electrical conductivity is comparatively large. Here, the maximum value of the electrical conductivity is 6.44 S/cm under the condition where the proportion of the flow rate of the oxygen gas is 0 volume %, that is, under the condition where only the argon gas is used as the film-forming gas. The minimum value of the electrical conductivity is 4.19×10⁻¹¹ S/cm under the condition where the proportion of the flow rate of the oxygen gas is 100 volume %, that is, under the condition where only the oxygen gas is used as the film-forming gas.

For formation of the first oxide semiconductor region serving as an active layer and the second oxide semiconductor region having lower electrical conductivity than the first oxide semiconductor region and serving as a protective layer for the active layer, the conditions of the proportion of the flow rate of the oxygen gas are differentiated from each other at around 70 volume % as a boundary, where gradient of the electrical conductivity is slightly steep in a graph of FIG. 12, whereby difference in the electrical conductivity between the first oxide semiconductor region and the second oxide semiconductor region can be made large. For example, in Embodiments 1 to 4, when the In—Ga—Zn—O-based non-single-crystal film used for the first oxide semiconductor region 103 is formed, the proportion of the flow rate of the oxygen gas is preferably set to lower than 70 volume %, that is, the electrical conductivity is preferably higher than 1.0×10⁻⁸ S/cm. In addition, when the In—Ga—Zn—O-based non-single-crystal film used for the second oxide semiconductor region 104 having lower electrical conductivity than the first oxide semiconductor region is formed, the proportion of the flow rate of the oxygen gas is preferably set to 70 volume % or higher, that is, the electrical conductivity is preferably 1.0×10⁻⁸ S/cm or lower. Note that, since the buffer layers 301 a and 301 b described in Embodiment 3 preferably have higher electrical conductivity than the first oxide semiconductor region 103, the proportion of the flow rate of the oxygen gas is preferably set to lower than 10 volume %, that is, the electrical conductivity is preferably higher than 1.0×10⁻³ S/cm.

This application is based on Japanese Patent Application serial No. 2008-304508 filed with Japan Patent Office on Nov. 28, 2008, the entire contents of which are hereby incorporated by reference. 

What is claimed is:
 1. A semiconductor device comprising: a first non-single crystalline oxide semiconductor layer comprising indium on an insulating surface, the first non-single crystalline oxide semiconductor layer having a first conductivity; a second non-single crystalline oxide semiconductor layer comprising indium over the first non-single crystalline oxide semiconductor layer, the second non-single crystalline oxide semiconductor layer having a second conductivity lower than the first conductivity; a gate electrode, wherein the gate electrode is overlapped with the first non-single crystalline oxide semiconductor layer and the second non-single crystalline oxide semiconductor layer; and an insulating film on the second non-single crystalline oxide semiconductor layer.
 2. A semiconductor device comprising: a first non-single crystalline oxide semiconductor layer comprising indium on an insulating surface, the first non-single crystalline oxide semiconductor layer having a first conductivity; a second non-single crystalline oxide semiconductor layer comprising indium over the first non-single crystalline oxide semiconductor layer, the second non-single crystalline oxide semiconductor layer having a second conductivity lower than the first conductivity; a gate electrode, wherein the gate electrode is overlapped with the first non-single crystalline oxide semiconductor layer and the second non-single crystalline oxide semiconductor layer; and an insulating film on the second non-single crystalline oxide semiconductor layer, wherein a concentration of sodium in the first non-single crystalline oxide semiconductor layer is 5×10¹⁹/cm³ or lower.
 3. A semiconductor device comprising: a first non-single crystalline oxide semiconductor layer comprising indium on an insulating surface, the first non-single crystalline oxide semiconductor layer having a first conductivity; a second non-single crystalline oxide semiconductor layer comprising indium over the first non-single crystalline oxide semiconductor layer, the second non-single crystalline oxide semiconductor layer having a second conductivity lower than the first conductivity; a gate electrode, wherein the gate electrode is overlapped with the first non-single crystalline oxide semiconductor layer and the second non-single crystalline oxide semiconductor layer; and an insulating film on the second non-single crystalline oxide semiconductor layer; a source electrode in electrical contact with the first non-single crystalline oxide semiconductor layer through a first buffer region having n-type conductivity; a drain electrode in electrical contact with the first non-single crystalline oxide semiconductor layer through a second buffer region having n-type conductivity, wherein each of the first buffer region and the second buffer region comprises crystal grains of an oxide semiconductor material comprising indium.
 4. A display device comprising: a gate electrode over a substrate; a gate insulating film over the gate electrode; a first non-single crystalline oxide semiconductor layer comprising indium over the gate electrode with the gate insulating film interposed therebetween, the first non-single crystalline oxide semiconductor layer having a first conductivity; a second non-single crystalline oxide semiconductor layer comprising indium over the first non-single crystalline oxide semiconductor layer, the second non-single crystalline oxide semiconductor layer having a second conductivity lower than the first conductivity; an insulating film on the second non-single crystalline oxide semiconductor layer; a source electrode in electrical contact with the first non-single crystalline oxide semiconductor layer through a first buffer region having n-type conductivity; a drain electrode in electrical contact with the first non-single crystalline oxide semiconductor layer through a second buffer region having n-type conductivity; and a pixel electrode in electrical contact with one of the source electrode and the drain electrode, wherein each of the first buffer region and the second buffer region comprises crystal grains of an oxide semiconductor material comprising indium and oxygen.
 5. A display device comprising: a gate electrode over a substrate; a gate insulating film over the gate electrode; a first non-single crystalline oxide semiconductor layer comprising indium over the gate electrode with the gate insulating film interposed therebetween, the first non-single crystalline oxide semiconductor layer having a first conductivity; a second non-single crystalline oxide semiconductor layer comprising indium over the first non-single crystalline oxide semiconductor layer, the second non-single crystalline oxide semiconductor layer having a second conductivity lower than the first conductivity; an insulating film on the second non-single crystalline oxide semiconductor layer; and a pixel electrode in electrical contact with the first non-single crystalline oxide semiconductor layer, wherein the gate electrode completely overlaps the first non-single crystalline oxide semiconductor layer and the second non-single crystalline oxide semiconductor layer.
 6. A display device comprising: a gate electrode over a substrate; a gate insulating film over the gate electrode; a first non-single crystalline oxide semiconductor layer comprising indium over the gate electrode with the gate insulating film interposed therebetween, the first non-single crystalline oxide semiconductor layer having a first conductivity; a second non-single crystalline oxide semiconductor layer comprising indium over the first non-single crystalline oxide semiconductor layer, the second non-single crystalline oxide semiconductor layer having a second conductivity lower than the first conductivity; a first insulating film comprising silicon and oxygen on the second non-single crystalline oxide semiconductor layer; a second insulating film comprising silicon and nitrogen over the first insulating film; and a planarizing insulating film comprising an organic material over the second insulating film; a pixel electrode over the planarizing insulating film, the pixel electrode being in electrical contact with the first non-single crystalline oxide semiconductor layer.
 7. The semiconductor device according to claim 1, wherein the insulating film comprises silicon and oxygen.
 8. The semiconductor device according to claim 1, further comprising a source electrode and a drain electrode, wherein the source electrode and the drain electrode are in contact with the first non-single crystalline oxide semiconductor layer.
 9. The semiconductor device according to claim 1, wherein each of the first non-single crystalline oxide semiconductor layer and the second non-single crystalline oxide semiconductor layer further comprises gallium and zinc.
 10. The semiconductor device according to claim 1, wherein a thickness of the first non-single crystalline oxide semiconductor layer is 10 nm to 300 nm.
 11. The semiconductor device according to claim 1, further comprising a gate insulating film comprising silicon and oxygen adjacent to the gate electrode.
 12. The semiconductor device according to claim 1, wherein the gate electrode is located below the first non-single crystalline oxide semiconductor layer.
 13. The semiconductor device according to claim 2, wherein the insulating film comprises silicon and oxygen.
 14. The semiconductor device according to claim 2, further comprising a source electrode and a drain electrode, wherein the source electrode and the drain electrode are in contact with the first non-single crystalline oxide semiconductor layer.
 15. The semiconductor device according to claim 2, wherein each of the first non-single crystalline oxide semiconductor layer and the second non-single crystalline oxide semiconductor layer further comprises gallium and zinc.
 16. The semiconductor device according to claim 2, wherein a thickness of the first non-single crystalline oxide semiconductor layer is 10 nm to 300 nm.
 17. The semiconductor device according to claim 2, further comprising a gate insulating film comprising silicon and oxygen adjacent to the gate electrode.
 18. The semiconductor device according to claim 2, wherein the gate electrode is located below the first non-single crystalline oxide semiconductor layer.
 19. The semiconductor device according to claim 3, wherein the insulating film comprises silicon and oxygen.
 20. The semiconductor device according to claim 3, wherein each of the first non-single crystalline oxide semiconductor layer and the second non-single crystalline oxide semiconductor layer further comprises gallium and zinc.
 21. The semiconductor device according to claim 3, wherein a thickness of the first non-single crystalline oxide semiconductor layer is 10 nm to 300 nm.
 22. The semiconductor device according to claim 3, further comprising a gate insulating film comprising silicon and oxygen adjacent to the gate electrode.
 23. The semiconductor device according to claim 3, wherein the gate electrode is located below the first non-single crystalline oxide semiconductor layer.
 24. The semiconductor device according to claim 3, wherein the oxide semiconductor material of the crystal grains further comprises gallium and zinc.
 25. The semiconductor device according to claim 3, further comprising a pixel electrode in electrical contact with one of the source electrode and the drain electrode.
 26. The display device according to claim 4, wherein the insulating film comprises silicon and oxygen.
 27. The display device according to claim 4, wherein each of the first non-single crystalline oxide semiconductor layer and the second non-single crystalline oxide semiconductor layer further comprises gallium and zinc.
 28. The display device according to claim 4, wherein a concentration of sodium in the first non-single crystalline oxide semiconductor layer is 5×10¹⁹/cm³ or lower.
 29. The display device according to claim 4, wherein a thickness of the first non-single crystalline oxide semiconductor layer is 10 nm to 300 nm.
 30. The display device according to claim 4, wherein the gate insulating film comprises silicon and oxygen.
 31. The display device according to claim 4, wherein the oxide semiconductor material of the crystal grains further comprises gallium and zinc.
 32. The display device according to claim 5, wherein the insulating film comprises silicon and oxygen.
 33. The display device according to claim 5, wherein each of the first non-single crystalline oxide semiconductor layer and the second non-single crystalline oxide semiconductor layer further comprises gallium and zinc.
 34. The display device according to claim 5, wherein a thickness of the first non-single crystalline oxide semiconductor layer is 10 nm to 300 nm.
 35. The display device according to claim 5, wherein the gate insulating film comprises silicon and oxygen.
 36. The display device according to claim 5, wherein a concentration of sodium in the first non-single crystalline oxide semiconductor layer is 5×10¹⁹/cm³ or lower.
 37. The display device according to claim 6, wherein each of the first non-single crystalline oxide semiconductor layer and the second non-single crystalline oxide semiconductor layer further comprises gallium and zinc.
 38. The display device according to claim 6, wherein a thickness of the first non-single crystalline oxide semiconductor layer is 10 nm to 300 nm.
 39. The display device according to claim 6, wherein a concentration of sodium in the first non-single crystalline oxide semiconductor layer is 5×10¹⁹/cm³ or lower.
 40. The semiconductor device according to claim 1, wherein a carrier concentration of the first non-single crystalline oxide semiconductor layer is lower than 1×10¹⁷/cm³.
 41. The semiconductor device according to claim 3, wherein the carrier concentration of the first buffer region and the second region is 1×10¹⁸/cm³ or higher.
 42. The semiconductor device according to claim 1, wherein the conductivity of the non-single crystalline second oxide semiconductor layer is 1×10⁻⁸ S/cm or lower. 